Calculating worst-case gate delays due to dominant capacitance coupling

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 46-51

  Dartu, Florentin ^a   Pileggi, Lawrence T ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CAPACITANCE; COUPLED CIRCUITS; ELECTRIC DELAY LINES; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

CAPACITANCE COUPLING; GATE DELAY; GATE LEVEL MODEL;

GATES (TRANSISTOR);

EID: 0030686019     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266033     Document Type: Conference Paper

References (14)