Analytical delay models for VLSI interconnects under ramp input

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 30-36

  Kahng, Andrew B ^a   Masuko, Kei ^a   Muddu, Sudhakar ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; PARAMETER ESTIMATION; SEMICONDUCTOR DEVICE MODELS; TIME VARYING NETWORKS; TRANSFER FUNCTIONS; TREES (MATHEMATICS);

ELMORE DELAY MODEL; RESISTANCE INDUCTANCE CAPACITANCE (RLC) INTERCONNECTIONS; SOFTWARE PACKAGE SPICE;

VLSI CIRCUITS;

EID: 0030386722     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)