A comprehensive delay macro modeling for submicrometer CMOS logics

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 1, 1999, Pages 42-55

  Daga, Jean Michel ^a   Auvergne, Daniel ^b  

^a ATMEL   (France)

^b LIRMM   (France)

Author keywords

Delay model; Input vector dependent; Input to output coupling; Short circuit; Submicronic CMOS

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC INVERTERS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; SHORT CIRCUIT CURRENTS;

ELECTRICAL SIMULATORS; SERIAL ARRAY REDUCTION TECHNIQUE; SUBMICROMETER RANGE;

CMOS INTEGRATED CIRCUITS;

EID: 0032649954     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.736655     Document Type: Article

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