CMOS gate delay models for general RLC loading

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 224-229

  Arunachalam, Ravishankar ^a   Dartu, Florentin ^a   Pileggi, Lawrence T ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; ELECTRIC LOADS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); MATHEMATICAL MODELS;

THEVENIN EQUIVALENT CEFF MODELS;

CMOS INTEGRATED CIRCUITS;

EID: 0031333601     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)