SunFloor 3D: A tool for networks on chip topology synthesis for 3D systems on chips

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 9-14

  Seiculescu, Ciprian ^a   Murali, Srinivasan ^a,b   Benini, Luca ^a   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b INoCs   (Switzerland)

Author keywords

3D ICs; Networks on chip (NoC); Placement; Synthesis; Topology

Indexed keywords

D REGION; INTEGRATED CIRCUIT INTERCONNECTS; NETWORK-ON-CHIP; PROGRAMMABLE LOGIC CONTROLLERS; SYNTHESIS (CHEMICAL); THREE DIMENSIONAL INTEGRATED CIRCUITS; TOPOLOGY;

3-D ICS; APPLICATION PERFORMANCE; APPLICATION SPECIFIC; COMPARATIVE STUDIES; INTERCONNECT POWER; NETWORK-ON-CHIP(NOC); NETWORKS ON CHIPS; PLACEMENT;

INTEGRATED CIRCUIT DESIGN;

EID: 66549118557     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090625     Document Type: Conference Paper

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