3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections

IBM Journal of Research and Development

Volumn 52, Issue 6, 2008, Pages 611-622

  Sakuma, Katsuyuki ^a   Andry, Paul S ^b   Tsang, Cornelia K ^a   Wright, Steven L ^a   Dang, Bing ^a   Patel, Chirag S ^b   Webb, Bucknell C ^a   Maria, Joana ^c   Sprogis, Edmund J ^d   Kang, Sung K ^b   Polastre, Robert J ^b   Horton, Raymond R ^b   Knickerbocker, John U ^b  

^a IBM RESEARCH TOKYO   (Japan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^d IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIES; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATION; LEAD-FREE SOLDERS; OPTIMIZATION; SILICON WAFERS; STRUCTURAL OPTIMIZATION;

3D-CHIP STACKING TECHNOLOGY; ASSEMBLY PROCESS; FINE PITCH INTERCONNECTS; HIGH FLEXIBILITY; SOLDER INTERCONNECT; SOLDER INTERCONNECTS; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH SILICON VIAS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 61649128557     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2008.5388567     Document Type: Article

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