Characterization of micro-bump C4 interconnects for Si-carrier SOP applications

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 633-640

  Wright, S L ^a   Polastre, R ^a   Gan, H ^b   Buchwalter, L P ^a   Horton, R ^a   Andry, P S ^a   Sprogis, E ^b   Patel, C ^a   Tsang, C ^a   Knickerbocker, J ^a   Lloyd, J R ^a   Sharma, A ^a   Sri Jayantha, M S ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTACT RESISTANCE; MICRO-BUMP C4 INTERCONNECTS; SI-CARRIER TECHNOLOGY; SI-CHIPS;

ELECTRIC RESISTANCE; EUTECTICS; RELIABILITY; SILICON WAFERS; SOLDERING ALLOYS;

INTERCONNECTION NETWORKS;

EID: 33845598091     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645716     Document Type: Conference Paper

References (25)

1. Knickerbocker, J., et al, "Development of next-generation systeom-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection," IBM J. Res. Dev. 49(4/5), 2005, pp. 725-754.
2. Knickerbocker, J., et al, "Three dimensional silicon integration using fine-pitch interconnection, silicon processing, and silicon carrier packaging technology," Proc. IEEE Custom Integrated Circuits Conf., Sept. 2005 pp. 654-657.
3. DiGiacomo, G., J.S. Jaspal, "Reliability of Die-Level Interconnections", chap. 13, pp. 519-520, in Area Array Interconnection Handbook. Kluwer Academic (Boston, 2001), ed. Puttlitz, K.J, Totta, P.A.
4. Puttlitz, K.J., Stalter, K.A., Handbook of Lead-Free Solder Technology for Microelectronic Assemblies, Marcel Dekker (New York, 2004), pp. 272-273.
5. Jaspal, J.S., IBM Microelectronics Division, Hopewell Junction, NY, personal communication.
6. Ref. 4, p. 838.
7. th Electronic Components and Technology Conf., San Diego, CA, 2006.
8. Jang, S-Y., et al, "UBM (Under Bump Metallization) study for Pb-free electroplating bumping: Interface reaction and electromigration," Proc 52nd Electronic Components and Technology Conf, San Diego, CA, May 2002, pp. 1213-1220.
9. th Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2005, pp. 1407-1415.
10. th Electronic Components and Technology Conf, Las Vegas, NV, May 2004, pp. 49-57.
11. th Electronic Components and Technology Conf, Las Vegas, NV, May 2004, pp. 1952-1958.
12. Tu, K.N., "Recent advances on electromigration in very-large-scale-integration of interconnects," J. Applied Phys. 94(9) 2003, pp. 5451-5473.
13. th IEEE Conf. High Density Microsystem Design and Packaging Component Failure Analysis, June 2004, pp. 224-226.
14. st IEEE Semiconductor Thermal Measurement and Management Symp., San Jose, CA, March 2005, pp. 1-7.
15. th Int. Reliability Physics Symp., Orlando, FL, 2001 pp. 341-349.
16. Lee, K-D., Ho, P., "Statistical study for electromigration reliability in dual-damascene Cu interconnects," IEEE Trans. Dev. Mat. Reliability 4(2) pp. 237-245 2004.
17. th Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2005, pp. 1431-1436.
18. Lloyd, J.R. and Kitchin, J., "The electromigration failure distribution: The fine-line case," J. Appl. Phys. 69(4) pp. 2117-2127 1991.
19. DiGiacomo, G., Reliability of Electronic Packages and Semiconductor Devices. McGraw-Hill (New York, 1997).
20. ReliaSoft Corporation, Weibull ++.
21. QualiTau, Inc., MIRA.
22. Zeng, K., Tu, K.N., "Six cases of reliability study of Pb-free solder joints in electronic packaging technology," Mat. Sci. Eng. R38 (2002), pp. 55-105.
23. Lee, T. Y, et al, "Electromigration of eutectic SnPb and SnAgCu flip chip solder bumps and under-bump metallization," J. Appl. Phys. 90(9) pp. 4502-4508 2001.
24. Ding, M., et al, "A study of electromigration failure in Pb-free solder joints", Proc. 43th Int. Reliability Physics Symp., San Jose, CA 2005, pp. 518-523.
25. Ren, F., et al, "Effect of electromigration on mechanical behavior of solder joints", Proc. Int. Symp. Adv. Packaging Materials, March 2005, pp. 66-69.