Optimization for chip stack in 3-D packaging

IEEE Transactions on Advanced Packaging

Volumn 28, Issue 3, 2005, Pages 367-376

  Hara, Kazumi ^a   Kurashima, Yohei ^a   Hashimoto, Nobuaki ^a   Matsui, Kuniyasu ^a   Matsuo, Yoshihide ^a   Miyazawa, Ikuya ^b   Kobayashi, Tomonaga ^a   Yokoyama, Yoshihiko ^a   Fukazawa, Motohiko ^a  

^a SEIKO EPSON CORPORATION   (Japan)

^b Technology Development Division   (Japan)

Author keywords

Bonding; Multichip modules; Semiconductor device packaging; Wiring

Indexed keywords

BONDING; MATHEMATICAL MODELS; MULTICHIP MODULES; OPTIMIZATION; SEMICONDUCTOR DEVICES; STATIC RANDOM ACCESS STORAGE;

CHIP STACKING; SEMICONDUCTOR DEVICE PACKAGING;

ELECTRONICS PACKAGING;

EID: 24644516719     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2005.852978     Document Type: Article

References (10)

1. P. Ramm, A. Klumpp, R. Merkel, J. Weber, R. Wieland, A. Ostmann, and J. Wolf, "3-D system integration technologies," in Proc. MRS Spring Meeting, Linear Networks and Systems, W.-K. Chen, Ed., Belmont, CA, 1993, E5-6, pp. 123-135.
2. S. Yamamoto, K. Ito, T. Suemasu, and T. Takizawa, "Si through-hole interconnections filled with Au-Sn solder by molten metal suction method," in Proc. IEEE 16th Annu. Int. Conf. Micro Electro Mechanical Systems, 2003, pp. 642-645.
3. "ASET Annual Research Report," ASET, Tokyo, Japan, 2004.
4. I. Miyazawa, "Development of die level stacked packaging," in ICEPT, 2003, pp. 320-325.
5. S. Oh, T. Yonezawa, K. Kondo, M. Tomisaka, H. Yonemura, M. Hoshino, Y. Taguchi, and K. Takahashi, "Copper electroplating applied to foll high-aspect-ratio vias for application of three dimensional chip stacking," in Proc. ICEPT, 2003, pp. 244-249.
6. K. Hara, "The trend of packaging technology in Japan," in Proc. ISMP, Seoul, Korea, Sep. 24-25, 2003, pp. 173-190.
7. N. Tanaka, T. Sato, Y. Yamajii, and K. Takahashi, "Mechanical characterization of copper through-vias in three dimensional die stacked module," in Proc. 9th Symp. Microjoining and Assembly Technology in Electronics, Yokohama, Japan, Feb. 6-7, 2003, pp. 151-156.
8. Y. Akiyama, R. kajiwara, N. Tanaka, K. Tanida, M. Umemoto, Y. Tomita, M. Tago, and K. Takahashi, "Superfine pitch ultrasonic bonding technology on 3-D stacked LSI," in Proc. ICEPT, 2003, pp. 326-331.
9. Y. Akiyama, R. Kajiwara, K. Tanida, M. Umemoto, Y. Tomita, M. Tago, and K. Takahashi, "20 mm-pitch micro-bump bonding utilizing ultrasonic flip-chip technology," in Proc. Mate, Yokohama, Japan, Feb. 6-7, 2003, pp. 45-50.
10. A. Okuno, "Unique New Packaging Technology of Semiconductor by High Performance Encapsulation Epoxy Resin and VPES," in Proc. 5th Int. Conf. Electronic Packaging Technology, Oct. 28-30, 2003, pp. 245-251.