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Volumn 2006, Issue , 2006, Pages 415-421

System-on-Package (SOP) technology, characterization and applications

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL SILICON; FINE PITCH AREA ARRAY SOLDER INTERCONNECTIONS; MICROCHANNEL COOLING; SILICON PACKAGE; SYSTEM-ON-PACKAGE (SOP);

EID: 33845562490     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645680     Document Type: Conference Paper
Times cited : (26)

References (17)
  • 1
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    • Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
    • th ECTC, 2005. p. 1318.
    • (2005) th ECTC , pp. 1318
    • Patel, C.S.1
  • 2
    • 25844453501 scopus 로고    scopus 로고
    • Development of next-generation systeom-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection
    • J. U. Knickerbocker et al., "Development of next-generation systeom-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection," IBM J. Res. Dev. 49(4/5), 2005, pp. 725-754.
    • (2005) IBM J. Res. Dev. , vol.49 , Issue.4-5 , pp. 725-754
    • Knickerbocker, J.U.1
  • 3
    • 33845593337 scopus 로고    scopus 로고
    • Three dimensional silicon integration using fine-pitch interconnection, silicon processing, and silicon carrier packaging technology
    • Sept.
    • J. U. Knickerbocker et al, "Three dimensional silicon integration using fine-pitch interconnection, silicon processing, and silicon carrier packaging technology," Proc. IEEE Custom Integrated Circuits Conf, Sept. 2005 pp. 654-657.
    • (2005) Proc. IEEE Custom Integrated Circuits Conf , pp. 654-657
    • Knickerbocker, J.U.1
  • 4
    • 24644495782 scopus 로고    scopus 로고
    • Three dimensional system-in-package using stacked Si platform technology
    • AUGUST
    • V. Kripesh et al. "Three Dimensional System-in-Package using Stacked Si Platform Technology", IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 3, AUGUST 2005
    • (2005) IEEE Transactions on Advanced Packaging , vol.28 , Issue.3
    • Kripesh, V.1
  • 5
    • 10444260501 scopus 로고    scopus 로고
    • Assembly & reliability of flip chip solder joints using miniaturized Au/Sn bumps
    • th ECTC 2004.
    • th ECTC 2004
    • Hunter, M.1
  • 6
    • 0036928172 scopus 로고    scopus 로고
    • Electrical integrity of state-of-the-art 0.13 um SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
    • K.W. Guarini et al., "Electrical Integrity of State-of-the-Art 0.13 um SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication," IEDM Tech Dig., 943-945 (2002).
    • (2002) IEDM Tech Dig. , pp. 943-945
    • Guarini, K.W.1
  • 7
    • 33748533457 scopus 로고    scopus 로고
    • Three- dimensional integrated circuits
    • Manuscript submitted for 2006 publication
    • A. W. Topol et al. "Three- Dimensional Integrated Circuits," IBM J. Res. Dev., Manuscript submitted for 2006 publication.
    • IBM J. Res. Dev.
    • Topol, A.W.1
  • 12
    • 0035519086 scopus 로고    scopus 로고
    • Frequency-dependent losses on high-performance interconnections
    • A. Deutsch, et. al., "Frequency-Dependent Losses on High-Performance Interconnections," IEEE Tran. on Electromagnetic Compatibility, vol. 43, no. 4, pg. 446-465.
    • IEEE Tran. on Electromagnetic Compatibility , vol.43 , Issue.4 , pp. 446-465
    • Deutsch, A.1
  • 13
    • 33845584096 scopus 로고    scopus 로고
    • US Patent 6791133 B2
    • Mukta G. Farooq et al, US Patent 6791133 B2.
    • Farooq, M.G.1
  • 17
    • 25844500236 scopus 로고    scopus 로고
    • A practical implementation of silicon microchannel coolers for high power chips
    • E.G. Colgan et al., "A Practical Implementation of Silicon Microchannel Coolers for High Power Chips ", IEEE SEMITHERM 2005, pp. 1-7.
    • IEEE SEMITHERM 2005 , pp. 1-7
    • Colgan, E.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.