Self-assembly process for chip-to-wafer three-dimensional integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 836-841

  Fukushima, T ^a   Yamada, Y ^a   Kikuchi, H ^a   Tanaka, T ^a   Koyanagi, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECTION NETWORKS; SILICON WAFERS; THREE DIMENSIONAL COMPUTER GRAPHICS;

CHIP THINNING; STACKED CHIPS;

ELECTRONICS PACKAGING;

EID: 35348855658     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373895     Document Type: Conference Paper

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