3D chip stacking technology with low-volume lead-free interconnections

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 627-632

  Sakuma, K ^a   Andry, P S ^a   Dang, B ^a   Maria, J ^b   Tsang, C K ^a   Patel, C ^a   Wright, S L ^a   Webb, B ^a   Sprogis, E ^c   Kang, S K ^a   Polastre, R ^a   Horton, R ^a   Knickerbocker, J U ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

4-POINT PROBING METHOD; BONDING PARAMETERS; CHIP STACKING; LEAD FREE INTERCONNECT;

ANNEALING; HEAT SINKS; INTERCONNECTION NETWORKS; INTERMETALLICS; SCANNING ELECTRON MICROSCOPY; SHEAR STRENGTH; SOLDERING ALLOYS;

CHIP SCALE PACKAGES;

EID: 34547375250     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373862     Document Type: Conference Paper

References (12)

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