A CMOS-compatible process for fabricating electrical through-vias in silicon

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 831-837

  Andry, P S ^a   Tsang, C ^a   Sprogis, E ^b   Patel, C ^a   Wright, S L ^a   Webb, B C ^a   Buchwalter, L P ^a   Manzer, D ^a   Horton, R ^a   Polastre, R ^a   Knickerbocker, J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER BACK-END-OF-THE-LINE (BEOL); SYSTEM-LEVEL PERFORMANCE; SYSTEM-ON-PACKAGE (SOP);

ASSEMBLY; CHEMICAL VAPOR DEPOSITION; COPPER; ELECTRIC CONDUCTORS; ELECTRIC WIRING; ELECTRONICS PACKAGING; SILICON;

CMOS INTEGRATED CIRCUITS;

EID: 33845571282     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645754     Document Type: Conference Paper

References (10)

1. Knickerbocker, J. et al, "Three dimensional silicon integration using fine-pitch interconnection, silicon processing, and silicon carrier packaging technology," Proc. IEEE Custom Integrated Circuits Conf., Sept. 2005 pp. 654-657.
2. Takahashi, K et al., "Current Status of Research and Development for Three-Dimensional Chip Stacking Technology." Jpn. J. Appl.Phys 40 (2001), pp. 3032-3037.
3. Patel, C.S. et al. "Silicon Carrier with Deep Through Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver," Proceedings of the 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, 2005, pp. 1318-1324.
4. Nelson, Donald W. et al, "A 3D Interconnect Methodolgy Applied to iA32-class Architectures for Performance Improvement through RC Mitigation", Proc 2004 VMIC Conf, Waikoloa Beach, HI, October 2004, pp. 78-83.
5. Topol, Anna W. et al, "Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs)", International Electron Devices Meeting (IEDM) Technical Digest, Washington, DC. December, 2005, pp. 363-366.
6. Tanida, K. et al, "Ultra High-Density Chip Stacking Technology," Proc 53rd Electronic Components and Technology Conf, New Orleans, LA, 2003, pp. 1084 1089.
7. L. Larson and D. Jessie, "Advanaces in RF packaging technologies for next-generation wireless communications applications", Proc. IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2003, pp.323-330.
8. Knickerbocker, J. et al, "Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection," IBM J. Res. Dev. 49(4/5), 2005, pp. 725-754.
9. th Electronic Components and Technology Conf, San Diego, CA, 2006.
10. Manzer, D. et al, "High-speed electrical testing of multichip ceramic modules," IBM J. Res. Dev. 49(4/5), 2005, pp. 687-697