A discussion on how to define the tolerance for line-edge or linewidth roughness and its measurement methodology

IEEE Transactions on Semiconductor Manufacturing

Volumn 20, Issue 4, 2007, Pages 549-555

  Yamaguchi, Atsuko ^a   Steffen, Robert ^b,c   Kawada, Hiroki ^b   Iizumi, Takashi ^b   Sugimoto, Aritoshi ^b  

^a HITACHI LTD   (Japan)

^b HITACHI HIGH TECHNOLOGIES CORPORATION   (Japan)

^c Hitachi High Technologies Europe GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

GATE PATTERNS; I - V CURVES; LINE-WIDTH ROUGHNESS; LONG LINES; MEASUREMENT ACCURACIES; MEASUREMENT METHODOLOGIES; MOSFETS; PRACTICAL PROCEDURES; RANDOM IMAGES; SAMPLING INTERVALS; TARGET VALUES; THRESHOLD-VOLTAGE SHIFTS;

SCANNING ELECTRON MICROSCOPY; THRESHOLD VOLTAGE;

ROUGHNESS MEASUREMENT;

EID: 59849106477     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.907632     Document Type: Article

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