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Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4344, Issue 1, 2001, Pages 809-814

Experimental determination of the impact of polysilicon LER on sub-100 nm transistor performance

(9) Patterson, Kyle a Sturtevant, John L a Alvis, John a Benavides, Nancy a Bonser, Doug b Cave, Nigel a Nelson Thomas, Carla a Taylor, Bill a Turnquest, Karen b

a MOTOROLA INC (United States)

b ADVANCED MICRO DEVICES (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; GATES (TRANSISTOR); IMAGE ANALYSIS; LEAKAGE CURRENTS; POLYSILICON; SCANNING ELECTRON MICROSCOPY; SUBSTRATES;

LINE EDGE ROUGHNESS (LER);

PHOTORESISTS;

EID: 0034763365 PISSN: 0277786X EISSN: None Source Type: Journal
DOI: 10.1117/12.436808 Document Type: Article

Times cited : (27)

References (9)

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3
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5
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- Sturtevant, J.L.¹ Allgair, J.² Fu, C.-C.³ Green, K.G.⁴ Hershey, R.R.⁵ Kling, M.E.⁶ Litt, L.C.⁷ Lucas, K.D.⁸ Roman, B.J.⁹ Seligman, G.S.¹⁰ Schippers, M.¹¹

8
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- Computational electronics, 2000. Book of abstracts
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- Linton, T.¹ Shaofeng, Y.² Shaheed, R.³

9
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- Kyoto, Japan
- (1999) 1999 Silicon Nanoelectronics Workshop
- Linton, T.¹ Giles, M.² Packan, P.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.