Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 3, 2004, Pages 357-361

  Xiong, Shiying ^a   Bokor, Jeffrey ^a   Xiang, Qi ^b   Fisher, Philip ^b   Dudley, Ian ^b   Rao, Paula ^b   Wang, Haihong ^b   En, Bill ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Bulk MOSFET; Dopant diffusion; Gate line edge roughness; Process variations

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; ETCHING; FOURIER TRANSFORMS; LEAKAGE CURRENTS; LITHOGRAPHY; OPTIMIZATION; SCANNING ELECTRON MICROSCOPY;

BULK MOSFET; DOPANT DIFFUSION; GATE LINE EDGE ROUGHNESS; PROCESS VARIATIONS;

MOSFET DEVICES;

EID: 4344591506     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.831560     Document Type: Conference Paper

References (7)

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