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Study of gate line edge roughness effects in 50 nm bulk MOSFET devices
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Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
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Characterization of line-edge roughness in resist patterns and estimation of its effect on device performance
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Metrology of LER: Influence of line-edge roughness (LER) on transistor performance
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Determination of optimal parameters for CD-SEM measurement of line edge roughness
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B. D. Bunday, M. Bishop, D. McCormack, J. S. Villarrubia, A. E. Vladar, R. Dixson, T. Vorburger, and N. G. Orji, "Determination of Optimal Parameters for CD-SEM Measurement of Line Edge Roughness," Proc. SPIE 5375, 515-533 (2004).
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A simulation study of repeatability and bias in the CD-SEM
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CD-SEM measurement of line edge roughness test patterns for 193 nm lithography
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