NBTI resilient circuits using adaptive body biasing

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2008, Pages 285-290

  Qi, Zhenyu ^a   Stan, Mircea R ^a  

^a University of Virginia   (United States)

Author keywords

Body biasing; NBTI; Reliability

Indexed keywords

DEGRADATION; LAKES; MILITARY OPERATIONS; RELIABILITY; THERMODYNAMIC STABILITY; VLSI CIRCUITS;

65NM TECHNOLOGIES; ADAPTIVE BODY BIASING; ADVANCED TECHNOLOGIES; BODY BIASING; DEVICE LIFETIMES; IN-SITU; LOW AREAS; LOW POWERS; NBTI; NEGATIVE BIAS TEMPERATURE INSTABILITIES; ORDERS OF MAGNITUDES; RELIABILITY MONITORING; RELIABILITY MONITORS; RING OSCILLATORS; STATIC STRESSES; SYSTEM ERRORS; SYSTEM LIFE TIMES; VLSI DESIGNS; WORST CASES;

NEGATIVE TEMPERATURE COEFFICIENT;

EID: 56749109533     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366110.1366179     Document Type: Conference Paper

References (27)

1. PTM web site. http://www.eas.asu.edu/ ptm/
2. M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra. Circuit failure prediction and its application to transistor aging. In Proc. of VLSI Test Symposium, pages 277-286, 2007.
3. M. Agostinelli, S. Pae, W. Yang, C. Prasad, D. Kenche, S. Ramey, E. Snyder, S. Kashyap, and M. Jones. Random charging effects for PMOS NBTI in ultra-small gate area devices. In Proc. Annual International Reliability Physics Symposium, pages 529-532, 2005.
4. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. Predictive modeling of the NBTI effect for reliable design. In Proc. IEEE Custom Integrated Circuits Conference (CICC), pages 189-192, 2006.
5. D. T. Blaauw, C. Oh, V. Zolotov, and A. Dasgupta. Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22(1):39-48, Jan. 2003.
6. S. Borkar. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro, 25(6):10-16, Nov. 2005.
7. G. Chen, K. Y. Chuah, M. F. Li, D. S. Chan, C. H. Ang, J. Z. Zheng, Y. Jin, and D. L. Kwong. Dynamic NBTI of PMOS transistors and its impact on device lifetime. In Proc. Annual International Reliability Physics Symposium, pages 196-202, 2003.
8. D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, and K. Flautner. Razor: Circuit-level correction of timing errors for low-power operation. IEEE Micro, 24(10):10-20, Nov. 2005.
9. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitiative Approach, 3rd. edition. Elsevier Science Pte Ltd., 2003.
10. K. Kang, K. Kim, A. E. Islam, M. A. Alam, and K. Roy. Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQ measurement. In Proc. Design Automation Conf. (DAC), pages 358-363, 2007.
11. K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. Efficient transistor-level sizing technique under temporal performance degradation due to NBTI. In Proc. IEEE Int. Conf. on Computer Design (ICCD), pages 934-939, 2007.
12. E. Karl, D. Blaauw, D. Sylvester, and T. Mudge. Reliability modeling and management in dynamic microprocessor-based systems. In Proc. Design Automation Conf. (DAC), pages 1057-1060, 2006.
13. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar. Impact of nbti on sram read stability and design for reliability. In Proc. Int. Symposium, on Quality Electronic Design (ISQED), Mar. 2006.
14. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar. Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale lsi systems. In Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pages 559-564, 2006.
15. Z. Liu and B. W. McGaughy. Design tools for reliability analysis. In Proc. Design Automation Conf. (DAC), pages 182-187, 2006.
16. Z. Lu, J. Lach, M. R. Stan, and K. Skadron. Improved thermal management with reliability banking. IEEE Micro, 25(6):40-49, Nov. 2005.
17. J. G. Massey. NBTI: what we know and what we need to know - a tutorial addressing the current understanding and challenges for the future. In IEEE International Integrated Reliability Workshop Final Report, pages 199-211, 2004.
18. S. Mishra, M. Pecht, and D. L. Goodman. In-situ sensors for product reliability monitoring. Proceedings of SPIE, 4755:10-19, 2002.
19. S. Mitra. Circuit failure prediction enables robust system design resilience to aging and wearout. In IEEE International On-Line Testing Symposium, 2007.
20. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. In Proc. European Design and Test Conf. (DATE), pages 780-785, 2006.
21. J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J. Solid-State Circuits, 37(11):1396-1402, Nov. 2002.
22. R. Vattikonda, W. Wang, and Y. Cao. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In Proc. Design Automation Conf. (DAC), pages 1047-1052, 2006.
23. W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudula, F. Liu, and Y. Cao. The impact of NBTI on the performance of combinational and sequential circuits. In Proc. Design Automation Conf. (DAC), 2007.
24. X. Yang and K. Saluja. Combating nbti degradation via gate sizing. In Proc. Int. Symposium. on Quality Electronic Design (ISQED), pages 47-52, 2007.
25. Y. Zhang and M. Stan. Temperature-aware circuit design using adaptive body biasing. In Proceedings of the ACM Great Lakes symposium on VLSI (GLSVLSI), pages 84-89, 2007.
26. W. Zhao and Y. Cao. New generation of predictive technology model for sub-45nm early design exploration. In IEEE Trans. on Electron Devices, volume 53, pages 2816-2823, November 2006.
27. Q. Zhou and K. Mohanram. Gate sizing to radiation harden combinational logic. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(1):155-166, Jan. 2006.