Circuit failure prediction enables robust system design resilient to aging and wearout

Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium

Volumn , Issue , 2007, Pages 123-

  Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGING MECHANISMS; DATA COLLECTED; DELAY FAULTS; FAILURE PREDICTION; INTERNATIONAL (CO); LOW COSTS; NEGATIVE BIAS- TEMPERATURE-INSTABILITY (NBTI); ON LINE TESTING; PMOS TRANSISTORS; ROBUST SYSTEM DESIGN; SENSOR DESIGNS; SIMULATION RESULTS; SYSTEM OPERATIONS; SYSTEM PERFORMANCES; TEST CHIP PROTOTYPE; WORST-CASE DESIGN;

DETECTORS; ELECTRIC FAULT CURRENTS; ERRORS; FLIP FLOP CIRCUITS; FORECASTING; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; NETWORKS (CIRCUITS); SENSORS; THERMODYNAMIC STABILITY;

ERROR DETECTION;

EID: 46749142921     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2007.23     Document Type: Conference Paper

References (1)

1. Agarwal, M., B. Paul, M. Zhang and S. Mitra, "Circuit Failure Prediction and its Application to Transistor Aging," Proc. IEEE VLSI Test Symp., pp. 277-284, 2007.