Static electromigration analysis for on-chip signal interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 1, 2003, Pages 39-48

  Blaauw, David T ^a   Oh, Chanhee ^b   Zolotov, Vladimir ^b   Dasgupta, Aurobindo ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b MOTOROLA INC   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Circuit analysis; Circuit simulation; Computer aided design; Interconnect reliability; Physical design

Indexed keywords

APPROXIMATION THEORY; CHARGE TRANSFER; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CURRENT DENSITY; ELECTRIC CONNECTORS; ELECTRIC CURRENTS; ELECTROMIGRATION; SWITCHING;

SIGNAL INTERCONNECTS;

SYSTEMS ANALYSIS;

EID: 0037230705     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.805728     Document Type: Article

References (19)

1. I. A. Blech and J. Sello, "The failure of thin aluminum current-carrying strips on oxidized silicon," Phys. Failure Electron., vol. 5, pp. 496-505, 1966.
2. J. R. Black, "Mass transport of aluminum by momentum exchange with conduction electrons," in Proc. IEEE Int. Reliability Physics Symp., 1967, pp. 148-159.
3. _, "Electromigration failure modes in aluminum metallization for semiconductor devices," Proc. IEEE, vol. 57, pp. 1587-1594, Sept. 1969.
4. B. Liew, N. Cheung, and C. Hu, "Projecting interconnect electromigration lifetime for arbitrary current waveforms," in Proc. IEEE Trans. Electron. Devices, vol. 37, May 1990, pp. 1343-1351.
5. J.J. Clement, "Vacancy supersaturation model for electromigration failure under DC and pulsed DC stress," J. Applied Phys., vol. 91, pp. 4264-4268, May 1992.
6. M. Ting, J. S. May, W. R. Hunter, and J. W. McPherson, "AC electromigration characterization and modeling of multilayered interconnects," in Proc. IEEE Int. Reliability Physics Symp., 1993, pp. 311-316.
7. J. Tao, N. Cheng, and C, Hu, "An electromigration failure model for interconnects under pulsed and bidirectional current stressing," IEEE Trans. Electron. Devices, vol. 41, pp. 539-545, Apr. 1994.
8. J. R. Lloyd and R. H. Koch, "Study of electromigration-induced resistance and resistance decay in Al thin film conductors," in Proc. IEEE Int. Reliability Physics Symp., 1987.
9. J. M. Towner and E. P. van de Ven, "Aluminum electromigration under pulsed dc conditions," in Proc. IEEE Int. Reliability Physics Symp., 1983, pp. 36-39.
10. J. A. Maiz, "Characterization of electromigration under bidirectional and pulsed unidirectional currents," in Proc. IEEE Int. Reliability Physics Symp., 1988, pp. 220-228.
11. L. M. Ting, J. S. May, W. R. Hunter, and J. W. McPherson, "AC eletromigration characterization and modeling of multi-layered interconnects," in Proc. IEEE Int. Reliability Physics Symp., 1993, pp. 311-316.
12. J. Kitchin, "Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor," in Proc. Symp. VLSI Circuits, 1995, pp. 115-116.
13. S. Rochel, G. Steele, J. R. Lloyd, S. Z. Hussain, and D. Overhauser, "Full-Chip reliability analysis," in Proc. IEEE Int. Reliability Physics Symp., 1998, pp. 356-362.
14. J. J. Clement, S. P. Riege, R. Cvijetic, and C. V. Thompson, "Methodology for electromigration critical threshold design rule evaluation," IEEE Trans. Computer-Aided Design, vol. 18, pp. 576-581, May 1999.
15. C. C. Teng, Y.-K. Cheng, E. Rosenbaum, and S.-M. Kang, "iTEM: A temperature-dependent electromigration reliability diagnosis tool," IEEE Trans. Computer-Aided Design, vol. 16, pp. 882-893, Aug. 1997.
16. J. E. Hall, D. E. Hocevar, P. Yang, and M. J. McGraw, "SPIDER-A CAD system for modeling VLSI metallization patterns," IEEE Trans. Computer-Aided Design, vol. 36, pp. 1023-1031, Nov. 1978.
17. R. H. Tu, E. Rosenbaum, W. Y. Chan, C. C. Li, E. Miami, K. Quader, P. K. Ko, and C. Hu, "Berkeley reliability tools-BERT," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1524-1534, Oct. 1993.
18. D. F. Frost and K. F. Poole, "RELIANT: A reliability analysis tool for VLSI interconnects," IEEE J. Solid-State Circuits, vol. 24, pp. 458-462, Apr. 1989.
19. J. Qian, S. Pullela, and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Computer-Aided Design, pp. 1526-1555, Dec. 1994.