-
2
-
-
4444365711
-
Measurements and Analysis of SER-tolerant Latch in a 90-nm dual-V/sub T/CMOS Process
-
Hazucha, P., Karnik, T., Walstra, S., Bloechel, B., Tschanz, J.W., Maiz, J., Soumyanath, K., Dermer, G., Narendra, S., De, V., Borkar, S.: Measurements and Analysis of SER-tolerant Latch in a 90-nm dual-V/sub T/CMOS Process. IEEE Journal of Solid-State Circuits 39(9), 1536-1543 (2004)
-
(2004)
IEEE Journal of Solid-State Circuits
, vol.39
, Issue.9
, pp. 1536-1543
-
-
Hazucha, P.1
Karnik, T.2
Walstra, S.3
Bloechel, B.4
Tschanz, J.W.5
Maiz, J.6
Soumyanath, K.7
Dermer, G.8
Narendra, S.9
De, V.10
Borkar, S.11
-
3
-
-
9144234352
-
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
-
Karnik, T., Hazucha, P.: Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. IEEE Transactions on Dependable and Secure Computing 1(2), 128-143 (2004)
-
(2004)
IEEE Transactions on Dependable and Secure Computing
, vol.1
, Issue.2
, pp. 128-143
-
-
Karnik, T.1
Hazucha, P.2
-
4
-
-
0036931372
-
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
-
Shivakumar, P., Kistler, M., Keckler, S., Burger, D., Alvisi, L.: Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. In: Proc. of the International Conf. on Dependable Systems and Networks, pp. 289-398 (2002)
-
(2002)
Proc. of the International Conf. on Dependable Systems and Networks
, pp. 289-398
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.3
Burger, D.4
Alvisi, L.5
-
5
-
-
0032667728
-
IBM's S/390 G5 Microprocessor Design
-
Slegel, T., Averill, R., Check, M., Giamei, B., Krumm, B., Krygowski, C., Li, W., Liptay, J., MacDougall, J., McPherson, T., Navarro, J., Schwarz, E., Shum, K., Webb, C.: IBM's S/390 G5 Microprocessor Design. IEEE Micro 19(2), 12-23 (1999)
-
(1999)
IEEE Micro
, vol.19
, Issue.2
, pp. 12-23
-
-
Slegel, T.1
Averill, R.2
Check, M.3
Giamei, B.4
Krumm, B.5
Krygowski, C.6
Li, W.7
Liptay, J.8
MacDougall, J.9
McPherson, T.10
Navarro, J.11
Schwarz, E.12
Shum, K.13
Webb, C.14
-
6
-
-
15044360879
-
The architecture of tandem's nonstop system
-
ACM Press, New York
-
McEvoy, D.: The architecture of tandem's nonstop system. In: ACM 1981: Proceedings of the ACM 1981 conference, p. 245. ACM Press, New York (1981)
-
(1981)
ACM 1981: Proceedings of the ACM 1981 conference
, pp. 245
-
-
McEvoy, D.1
-
8
-
-
2642540033
-
Cache Scrubbing in Microprocessors: Myth or Necessity?
-
Mukherjee, S., Emer, J., Fossum, T., Reinhardt, S.: Cache Scrubbing in Microprocessors: Myth or Necessity? In: Proc. of the Pacific RIM International Symposium on Dependable Computing, pp. 37-42 (2004)
-
(2004)
Proc. of the Pacific RIM International Symposium on Dependable Computing
, pp. 37-42
-
-
Mukherjee, S.1
Emer, J.2
Fossum, T.3
Reinhardt, S.4
-
10
-
-
0036292677
-
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
-
ISCA
-
Sorin, D., Martin, M., Hill, M., Wood, D.: SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. In: Proc. of the International Symposium on Computer Architecture (ISCA) (2002)
-
(2002)
Proc. of the International Symposium on Computer Architecture
-
-
Sorin, D.1
Martin, M.2
Hill, M.3
Wood, D.4
-
12
-
-
20344403770
-
Montecito: A Dual-core, Dual-thread Itanium Processor
-
McNairy, C., Bhatia, R.: Montecito: A Dual-core, Dual-thread Itanium Processor. IEEE Micro 25(2), 10-20 (2005)
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 10-20
-
-
McNairy, C.1
Bhatia, R.2
-
13
-
-
20344374162
-
Niagara: A 32-way multithreaded sparc processor
-
Kongetira, P., Aingaran, K., Olukotun, K.: Niagara: A 32-way multithreaded sparc processor. IEEE Micro 25(2), 21-29 (2005)
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 21-29
-
-
Kongetira, P.1
Aingaran, K.2
Olukotun, K.3
-
14
-
-
0036504519
-
Power4 system design for high reliability
-
Bossen, D., Tendler, J., Reick, K.: Power4 system design for high reliability. IEEE Micro 22(2), 16-24 (2002)
-
(2002)
IEEE Micro
, vol.22
, Issue.2
, pp. 16-24
-
-
Bossen, D.1
Tendler, J.2
Reick, K.3
-
15
-
-
26444583353
-
-
Lattner, C., Adve, V.: The LLVM Compiler Framework and Infrastructure Tutorial. In: Eigenmann, R., Li, Z., Midkiff, S.P. (eds.) LCPC 2004. LNCS, 3602. Springer, Heidelberg (2005)
-
Lattner, C., Adve, V.: The LLVM Compiler Framework and Infrastructure Tutorial. In: Eigenmann, R., Li, Z., Midkiff, S.P. (eds.) LCPC 2004. LNCS, vol. 3602. Springer, Heidelberg (2005)
-
-
-
-
16
-
-
33646829087
-
SWIFT: Software Implemented Fault Tolerance
-
Reis, G.A., Chang, J., Vachharajani, N., Rangan, R., August, D.I.: SWIFT: Software Implemented Fault Tolerance. In: Proc. of the International Symposium on Code Generation and Optimization (CGO) (2005)
-
(2005)
Proc. of the International Symposium on Code Generation and Optimization (CGO)
-
-
Reis, G.A.1
Chang, J.2
Vachharajani, N.3
Rangan, R.4
August, D.I.5
-
17
-
-
0036287327
-
Detailed Design and Evaluation of Redundant Multithreading Alternatives
-
Washington, DC, USA, pp, IEEE Computer Society, Los Alamitos
-
Mukherjee, S.S., Kontz, M., Reinhardt, S.K.: Detailed Design and Evaluation of Redundant Multithreading Alternatives. In: Proc. of International Symposium on Computer Architecture, Washington, DC, USA, pp. 99-110. IEEE Computer Society, Los Alamitos (2002)
-
(2002)
Proc. of International Symposium on Computer Architecture
, pp. 99-110
-
-
Mukherjee, S.S.1
Kontz, M.2
Reinhardt, S.K.3
-
19
-
-
84968854658
-
Y-Branches: When You Come to a Fork in the Road, Take It
-
Wang, N., Fertig, M., Patel, S.: Y-Branches: When You Come to a Fork in the Road, Take It. In: Proc. of the International Conference on Parallel Architectures and Compilation Techniques (PACT) (2003)
-
(2003)
Proc. of the International Conference on Parallel Architectures and Compilation Techniques (PACT)
-
-
Wang, N.1
Fertig, M.2
Patel, S.3
-
20
-
-
54249089763
-
Non-uniform fault tolerance
-
WAR
-
Chang, J., Reis, G.A., Vachharajani, N., Rangan, R., August, D.: Non-uniform fault tolerance. In: Proceedings of the 2nd Workshop on Architectural Reliability (WAR) (2006)
-
(2006)
Proceedings of the 2nd Workshop on Architectural Reliability
-
-
Chang, J.1
Reis, G.A.2
Vachharajani, N.3
Rangan, R.4
August, D.5
-
21
-
-
85011384331
-
Evaluation of a 32-bit microprocessor with built-in concurrent error detection
-
Washington, DC, USA, p, IEEE Computer Society, Los Alamitos
-
Gaisler, J.: Evaluation of a 32-bit microprocessor with built-in concurrent error detection. In: FTCS 1997: Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS 1997), Washington, DC, USA, p. 42. IEEE Computer Society, Los Alamitos (1997)
-
(1997)
FTCS 1997: Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS
, pp. 42
-
-
Gaisler, J.1
-
22
-
-
54249151321
-
Shield: Cost-Effective Soft-Error Protection for Register Files
-
Montesinos, P., Liu, W., Torrellas, J.: Shield: Cost-Effective Soft-Error Protection for Register Files. In: Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC 2006) (2006)
-
(2006)
Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC
-
-
Montesinos, P.1
Liu, W.2
Torrellas, J.3
-
23
-
-
33845562664
-
In-register duplication: Exploiting narrow-width value for improving register file reliability
-
Washington, DC, USA, pp, IEEE Computer Society, Los Alamitos
-
Hu, J., Wang, S., Ziavras, S.G.: In-register duplication: Exploiting narrow-width value for improving register file reliability. In: DSN 2006: Proceedings of the International Conference on Dependable Systems and Networks (DSN 2006), Washington, DC, USA, pp. 281-290. IEEE Computer Society, Los Alamitos (2006)
-
(2006)
DSN 2006: Proceedings of the International Conference on Dependable Systems and Networks (DSN
, pp. 281-290
-
-
Hu, J.1
Wang, S.2
Ziavras, S.G.3
-
24
-
-
27544438520
-
Design and Evaluation of Hybrid Fault-Detection Systems
-
ISCA
-
Reis, G.A., Chang, J., Vachharajani, N., Rangan, R., August, D.I., Mukherjee, S.S.: Design and Evaluation of Hybrid Fault-Detection Systems. In: Proc. of the International International Symposium on Computer Architecture (ISCA) (2005)
-
(2005)
Proc. of the International International Symposium on Computer Architecture
-
-
Reis, G.A.1
Chang, J.2
Vachharajani, N.3
Rangan, R.4
August, D.I.5
Mukherjee, S.S.6
-
25
-
-
54249145996
-
Configurable Transient Fault Detection via Dynamic Binary Translation
-
WAR
-
Reis, G.A., Chang, J., August, D.I., Cohn, R., Mukherjee, S.S.: Configurable Transient Fault Detection via Dynamic Binary Translation. In: Proceedings of the 2nd Workshop on Architectural Reliability (WAR) (2006)
-
(2006)
Proceedings of the 2nd Workshop on Architectural Reliability
-
-
Reis, G.A.1
Chang, J.2
August, D.I.3
Cohn, R.4
Mukherjee, S.S.5
-
26
-
-
31944440969
-
Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation
-
Luk, C., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V.J., Hazelwood, K.: Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In: Proc. of the International Conference on Programming Language Design and Implementation (PLDI) (2005)
-
(2005)
Proc. of the International Conference on Programming Language Design and Implementation (PLDI)
-
-
Luk, C.1
Cohn, R.2
Muth, R.3
Patil, H.4
Klauser, A.5
Lowney, G.6
Wallace, S.7
Reddi, V.J.8
Hazelwood, K.9
-
27
-
-
84944403418
-
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
-
Washington, DC, USA, p, IEEE Computer Society, Los Alamitos
-
Mukherjee, S.S., Weaver, C., Emer, J., Reinhardt, S.K., Austin, T.: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. In: MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium onMicroarchitecture, Washington, DC, USA, p. 29. IEEE Computer Society, Los Alamitos (2003)
-
(2003)
MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium onMicroarchitecture
, pp. 29
-
-
Mukherjee, S.S.1
Weaver, C.2
Emer, J.3
Reinhardt, S.K.4
Austin, T.5
-
29
-
-
85019407607
-
Software-controlled fault tolerance
-
Reis, G.A., Chang, J., Vachharajani, N., Rangan, R., August, D.I., Mukherjee, S.S.: Software-controlled fault tolerance. ACM Trans. Archit. Code Optim. 2(4), 366-396 (2005)
-
(2005)
ACM Trans. Archit. Code Optim
, vol.2
, Issue.4
, pp. 366-396
-
-
Reis, G.A.1
Chang, J.2
Vachharajani, N.3
Rangan, R.4
August, D.I.5
Mukherjee, S.S.6
-
30
-
-
84963800757
-
A Source-to-Source Compiler for Generating Dependable Software
-
Rebaudengo, M., Reorda, M.S., Violante, M., Torchiano, M.: A Source-to-Source Compiler for Generating Dependable Software. In: IEEE International Workshop on Source Code Analysis and Manipulation (SCAM), pp. 35-44 (2001)
-
(2001)
IEEE International Workshop on Source Code Analysis and Manipulation (SCAM)
, pp. 35-44
-
-
Rebaudengo, M.1
Reorda, M.S.2
Violante, M.3
Torchiano, M.4
-
31
-
-
0036507790
-
Error Detection by Duplicated Instructions in Super-scalar Processors
-
Oh, N., Shirvani, P., McCluskey, E.J.: Error Detection by Duplicated Instructions in Super-scalar Processors. IEEE Transactions on Reliability 51(1), 63-75 (2002)
-
(2002)
IEEE Transactions on Reliability
, vol.51
, Issue.1
, pp. 63-75
-
-
Oh, N.1
Shirvani, P.2
McCluskey, E.J.3
-
32
-
-
33750415121
-
Automatic Instruction-Level Software-Only Recovery
-
Washington, DC, USA, pp, IEEE Computer Society, Los Alamitos
-
Chang, J., Reis, G.A., August, D.I.: Automatic Instruction-Level Software-Only Recovery. In: DSN 2006: Proceedings of the International Conference on Dependable Systems and Networks (DSN 2006), Washington, DC, USA, pp. 83-92. IEEE Computer Society, Los Alamitos (2006)
-
(2006)
DSN 2006: Proceedings of the International Conference on Dependable Systems and Networks (DSN
, pp. 83-92
-
-
Chang, J.1
Reis, G.A.2
August, D.I.3
|