-
1
-
-
0032684765
-
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
-
M. Nicolaidis, "Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies", IEEE VLSI Test Symposium, 1999, pp. 86-94.
-
(1999)
IEEE VLSI Test Symposium
, pp. 86-94
-
-
Nicolaidis, M.1
-
2
-
-
33847113086
-
Cost Reduction and Evolution of a Temporary Faults Detecting Techniques
-
L. Anghel, M. Nicolaidis, "Cost Reduction and Evolution of a Temporary Faults Detecting Techniques", IEEE Design Automation and Test in Europe, 2000, pp. 591-598.
-
(2000)
IEEE Design Automation and Test in Europe
, pp. 591-598
-
-
Anghel, L.1
Nicolaidis, M.2
-
3
-
-
0021471901
-
Fault Tolerance by Design Diversity: Concepts and Experiments
-
Aug
-
A. Avizienis, J. P. J. Kelly, "Fault Tolerance by Design Diversity: Concepts and Experiments", IEEE Computer, Aug. 1984, pp. 67-80.
-
(1984)
IEEE Computer
, pp. 67-80
-
-
Avizienis, A.1
Kelly, J.P.J.2
-
4
-
-
0022252695
-
The N-Version Approach to Fault-Tolerant Software
-
Dec
-
A. Avizienis, "The N-Version Approach to Fault-Tolerant Software," IEEE Trans. On Software Engineering, Vol. 11, No. 12, Dec. 1985, pp. 1491-1501
-
(1985)
IEEE Trans. on Software Engineering
, vol.11
, Issue.12
, pp. 1491-1501
-
-
Avizienis, A.1
-
5
-
-
0016522101
-
System Structure for Software Fault Tolerant
-
Jun
-
B. Randell, "System Structure for Software Fault Tolerant," IEEE Trans. On Software Engineering, Vol. 1, No. 2, Jun. 1975, pp. 220-232.
-
(1975)
IEEE Trans. on Software Engineering
, vol.1
, Issue.2
, pp. 220-232
-
-
Randell, B.1
-
6
-
-
0034260103
-
Software-Implemented EDAC Protection Against SEUs
-
June
-
P. Shirivani, N. Saxena, E. J. McCluskey, "Software-Implemented EDAC Protection Against SEUs", IEEE Transactions on Reliability, Special Issue on Fault-Tolerant VLSI Systems, June 2000.
-
(2000)
IEEE Transactions on Reliability, Special Issue on Fault-Tolerant VLSI Systems
-
-
Shirivani, P.1
Saxena, N.2
McCluskey, E.J.3
-
7
-
-
0021439162
-
Algorithm-Based Fault Tolerance for Matrix Operations
-
Dec
-
K. H. Huang, J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations", IEEE Transaction on Computers, vol. 33, Dec 1984, pp. 518-528.
-
(1984)
IEEE Transaction on Computers
, vol.33
, pp. 518-528
-
-
Huang, K.H.1
Abraham, J.A.2
-
8
-
-
0032674982
-
Design and Evaluation of System-level Checks for On-line Control Flow Error Detection
-
Jun
-
Z. Alkhalifa, V.S.S. Nair, N. Krishnamurthy, J.A. Abraham, "Design and Evaluation of System-level Checks for On-line Control Flow Error Detection," IEEE Trans. On Parallel and Distributed Systems, Vol. 10, No. 6, Jun. 1999, pp. 627-641.
-
(1999)
IEEE Trans. on Parallel and Distributed Systems
, vol.10
, Issue.6
, pp. 627-641
-
-
Alkhalifa, Z.1
Nair, V.S.S.2
Krishnamurthy, N.3
Abraham, J.A.4
-
9
-
-
0000347178
-
An Approach to Concurrent Control Flow Checking
-
March
-
S.S. Yau, F.-C. Chen, "An Approach to Concurrent Control Flow Checking," IEEE Trans. On Software Engineering, Vol. 6, No. 2, March 1980, pp. 126-137.
-
(1980)
IEEE Trans. on Software Engineering
, vol.6
, Issue.2
, pp. 126-137
-
-
Yau, S.S.1
Chen, F.-C.2
-
11
-
-
0033349322
-
Soft-error Detection through Software Fault-Tolerance techniques
-
M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante, "Soft-error Detection through Software Fault-Tolerance techniques", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1999, pp. 210-218.
-
(1999)
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
, pp. 210-218
-
-
Rebaudengo, M.1
Sonza Reorda, M.2
Torchiano, M.3
Violante, M.4
-
12
-
-
33745489873
-
Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
-
M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco, "Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures", IEEE International On-Line Lest Workshop, 2000.
-
(2000)
IEEE International On-Line Lest Workshop
-
-
Rebaudengo, M.1
Sonza Reorda, M.2
Violante, M.3
Cheynet, P.4
Nicolescu, B.5
Velazco, R.6
-
13
-
-
0034450434
-
Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
-
December
-
P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante, "Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors", IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236.
-
(2000)
IEEE Transactions on Nuclear Science
, vol.47
, Issue.6
, pp. 2231-2236
-
-
Cheynet, P.1
Nicolescu, B.2
Velazco, R.3
Rebaudengo, M.4
Sonza Reorda, M.5
Violante, M.6
-
14
-
-
0034590511
-
A C/C++ Source-to-Source Compiler for Dependable Applications
-
June
-
A. Benso, S. Chiusano, P. Prinetto, L. Tagliaferro, "A C/C++ Source-to-Source Compiler for Dependable Applications", International Conference on Dependable Systems and Networks, June 2000.
-
(2000)
International Conference on Dependable Systems and Networks
-
-
Benso, A.1
Chiusano, S.2
Prinetto, P.3
Tagliaferro, L.4
-
15
-
-
0033892257
-
Two Program Comprehension Tools for Automatic Parallelization
-
January-March
-
B. di Martino, C. W. Kessler, "Two Program Comprehension Tools for Automatic Parallelization", IEEE Concurrency, Vol. 8, No. 1, January-March 2000
-
(2000)
IEEE Concurrency
, vol.8
, Issue.1
-
-
Di Martino, B.1
Kessler, C.W.2
-
16
-
-
84963922774
-
-
ftp://iecc.com/pub/file/c-grammar.gz
-
-
-
-
17
-
-
0004072686
-
-
Adison-Wesley
-
A. Aho, R. Sethi, J. Ullman, "Compilers - Principles, Techniques and Tools", Adison-Wesley, 1986.
-
(1986)
Compilers - Principles, Techniques and Tools
-
-
Aho, A.1
Sethi, R.2
Ullman, J.3
-
18
-
-
33746890642
-
An Integrated HW and SW Fault Injection Environment for Real-Time Systems
-
A. Benso, M. Rebaudengo, M. Sonza Reorda, P.L. Civera, "An Integrated HW and SW Fault Injection Environment for Real-Time Systems", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1998, pp. 117-122.
-
(1998)
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
, pp. 117-122
-
-
Benso, A.1
Rebaudengo, M.2
Sonza Reorda, M.3
Civera, P.L.4
|