3-D topologies for networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 10, 2007, Pages 1081-1090

  Pavlidis, Vasilis F ^a,b   Friedman, Eby G ^a,b  

^a IEEE

^b University of Rochester   (United States)

Author keywords

3 D circuits; 3 D integrated circuits (ICs); 3 D integration; Networks on chip (NoC); Topologies

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); CONSTRAINT THEORY; ELECTRIC POWER UTILIZATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; THREE DIMENSIONAL;

ANALYTIC MODELS; NETWORKS ON CHIPS (NOC);

TOPOLOGY;

EID: 34648854453     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893649     Document Type: Article

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