Composable lightweight processors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 381-393

  Kim, Changkyu ^a,c   Sethumadhavan, Simha ^b   Gulati, Divya ^b   Burger, Doug ^b   Govindan, M S ^b   Ranganathan, Nitya ^b   Keckler, Stephen W ^b  

^a INTEL CORPORATION   (United States)

^b University of Texas at Austin   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STRUCTURES; NANOTECHNOLOGY; PROGRAM PROCESSORS;

ARCHITECTURAL APPROACH; AVERAGE PERFORMANCE; AVERAGE POWER; CHIP MULTI PROCESSOR (CMP); CMP ARCHITECTURES; DATA GRAPHS; DESIGN TIME; IN BETWEEN; INSTRUCTION-LEVEL PARALLELISM (ILP); INTERNATIONAL SYMPOSIUM; LOW POWERS; MICRO ARCHITECTURES; MONOLITHIC STRUCTURES; SIMULATION RESULTS; SINGLE THREADED PROCESSORS; SINGLE-THREADED; THREAD-LEVEL PARALLELISM (TLP);

POWER SPECTRUM;

EID: 47349132683     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.41     Document Type: Conference Paper

References (35)

1. D. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proceedings of the 32nd Annual International Symposium on Microarchitecture, pages 248-261, 1999.
2. D. H. Albonesi, R. Balasubramonian, S. Dropsho, S. Dwarkadas, E. G. Friedman, M. C. Huang, V. Kursun, G. Magklis, M. L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, and S. Schuster. Dynamically tuning processor resources with adaptive processing. IEEE Computer, 36(12):49-58, 2003.
3. R. I. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 218-229, 2001.
4. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, 2000.
5. S. Browne, J. Dongarra, N. Garner, K. S. London, and P. Mucci. A scalable cross-platform infrastructure for application performance tuning using hardware counters. In Proceedings of the 2000 conference on Supercomputing, page 42, 2000.
6. D. Burger, S. Keckler, K. McKinley, M. Dahlin, L. John, C. Lin, C. Moore, J. Burrill, R. McDonald, and W. Yoder. Scaling to the end of silicon with EDGE architectures. IEEE Computer, 37(7), 2004.
7. J. Diamond, B. Robatmilli, S. W. Kecker, R. van de Geign, K. Goto, and D. Burger. High performance linear algebra on a spatially distributed processor. Technical Report TR-07-49, Department of Computer Sciences, The University of Texas at Austin, 2007.
8. D. Folegnani and A. González. Energy-effective issue logic. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 230-239, 2001.
9. K. Goto and R. A. van de Geijn. Anatomy of a high-performance matrix multiplication. ACMTransactions on Mathematical Software, 34(3), 2008.
10. L. Hammond, B. A. Hubbert, M. Siu, M. K. Prabhu, M. K. Chen, and K. Olukotun. The Stanford Hydra CMP. IEEE Micro, 20(2), 2000.
11. T. Ibaraki and N. Katoh. Resource allocation problems: Algorithmic approaches. MIT Press, 1988.
12. E. Ipek, M. Kirman, N. Kirman, and J. F. Martínez. Core Fusion: Accommodating software diversity in chip multiprocessors. In Proceedings of the 34th International Symposium on Computer Architecture, pages 186-197, 2007.
13. R. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, 1999.
14. C. Kim, D. Burger, and S. W. Keckler. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 211-222, 2002.
15. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded sparc processor. IEEE Micro, 25(2), 2005.
16. V. Krishnan and J. Torrellas. A chip-multiprocessor architecture with speculative multithreading. IEEE Transactions on Computers, 48(9):866-880, 1999.
17. R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In Proceedings of the 36th Annual International Symposium on Microarchitecture, pages 81-92, 2003.
18. R. Kumar, N. P. Jouppi, and D. M. Tullsen. Conjoined-core chip multiprocessing. In Proceedings of the 37th Annual International Symposium on Microarchitecture, pages 195-206, 2004.
19. R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-isa heterogeneous multi-core architectures for multi-threaded workload performance. In Proceedings of the 31st International Symposium on Computer Architecture, pages 64-75, 2004.
20. F. Latorre, J. González, and A. González. Back-end assignment schemes for clustered multithreaded processors. In Proceedings of the 17th Annual International Conference on Supercomputing, pages 316-325, 2004.
21. G. Ottoni, R. Rangan, A. Stoler, and D. I. August. Automatic thread extraction with decoupled software pipelining. In Proceedings of the 38th Annual International Symposium on Microarchitecture, pages 105-118, 2005.
22. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 90-101, 2001.
23. R. M. Rabbah, I. Bratt, K. Asanović, and A. Agarwal. Versatility and versabench: A new metric and a benchmark suite for flexible architectures. Massachusetts Institute of Technology Technical Report MIT-LCS-TM-646, 2004.
24. P. Racunas and Y. N. Patt. Partitioned first-level cache design for clustered microarchitectures. In Proceedings of the 17th Annual International Conference on Supercomputing, pages 22-31, 2003.
25. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S.W. Keckler, and C. R. Moore. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In Proceedings of the 30th International Symposium on Computer Architecture, pages 422-433, 2003.
26. K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M. S. S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S. W. Keckler, and D. Burger. Distributed microarchitectural protocols in the TRIPS prototype processor. In Proceedings of the 39th Annual International Symposium on Microarchitecture, pages 480-491, 2006.
27. S. Sethumadhavan, F. Roesner, J. S. Emer, D. Burger, and S. W. Keckler. Late-Binding: Enabling unordered load-store queues. In Proceedings of the 34th International Symposium on Computer Architecture, pages 347-357, 2007.
28. T. Sherwood, E. Perelman, and B. Calder. Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 3-14, 2001.
29. B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner. Power5 system microarchitecture. IBM Journal of Research and Development, 49(4-5):505-522, 2005.
30. A. Snavely and D. M. Tullsen. Symbiotic jobscheduling for a simultaneous multithreaded processor. In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 234-244, 2000.
31. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 414-425, 1995.
32. S. Swanson, K. Michelson, A. Schwerin, and M. Oskin. Wavescalar. In Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, pages 291-302, 2003.
33. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 392-403, 1995.
34. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring it all to software: Raw machines. IEEE Computer, 30(9):86-93, 1997.
35. H. Zhong, S. A. Lieberman, and S. A. Mahlke. Extending multicore architectures to exploit hybrid parallelism in single-thread applications. In Proceedings of the International Conference on High Performance Computer Architecture, pages 25-36, 2007.