-
1
-
-
84944045350
-
Design and implementation of an efficient thread partitioning algorithm
-
J. N. Amaral, G. Gao, E. D. Kocalar, P. O'Neill, and X. Tang. Design and implementation of an efficient thread partitioning algorithm. In Proceedings of the International Symposium on High Performance Computing, pages 252-259, 2000.
-
(2000)
Proceedings of the International Symposium on High Performance Computing
, pp. 252-259
-
-
Amaral, J.N.1
Gao, G.2
Kocalar, E.D.3
O'Neill, P.4
Tang, X.5
-
2
-
-
0031594006
-
Integrated predication and speculative execution in the IMPACT EPIC architecture
-
June
-
D. I. August, D. A. Connors, S. A. Mahlke, J. W. Sias, K. M. Crozier, B. Cheng, P. R. Eaton, Q. B. Olaniran, and W. W. Hwu. Integrated predication and speculative execution in the IMPACT EPIC architecture. In Proceedings of the 25th International Symposium on Computer Architecture, pages 227-237, June 1998.
-
(1998)
Proceedings of the 25th International Symposium on Computer Architecture
, pp. 227-237
-
-
August, D.I.1
Connors, D.A.2
Mahlke, S.A.3
Sias, J.W.4
Crozier, K.M.5
Cheng, B.6
Eaton, P.R.7
Olaniran, Q.B.8
Hwu, W.W.9
-
3
-
-
84944390453
-
Beating in-order stalls with 'flea-flicker' two-pass pipelining
-
December
-
R. D. Barnes, E. M. Nystrom, J. W. Sias, S. J. Patel, N. Navarro, and W. W. Hwu. Beating in-order stalls with 'flea-flicker' two-pass pipelining. In Proceedings of the 36th International Symposium on Microarchitecture, December 2003.
-
(2003)
Proceedings of the 36th International Symposium on Microarchitecture
-
-
Barnes, R.D.1
Nystrom, E.M.2
Sias, J.W.3
Patel, S.J.4
Navarro, N.5
Hwu, W.W.6
-
6
-
-
0009868048
-
-
PhD thesis, Department of Computer Science, University of Illinois, Urbana, IL
-
D.-K. Chen. Compiler Optimizations for Parallel Loops with Finegrained Synchronization, PhD thesis, Department of Computer Science, University of Illinois, Urbana, IL, 1994.
-
(1994)
Compiler Optimizations for Parallel Loops with Finegrained Synchronization
-
-
Chen, D.-K.1
-
9
-
-
0036959649
-
A stream compiler for communication-exposed architectures
-
M. I. Gordon, W. Thies, M. Karczmarek, J. Lin, A. S. Meli, A. A. Lamb, C. Leger, J. Wong, H. Hoffmann, D. Maze, and S. Amarasinghe. A stream compiler for communication-exposed architectures. In ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, pages 291-303, 2002.
-
(2002)
ASPLOS-X: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 291-303
-
-
Gordon, M.I.1
Thies, W.2
Karczmarek, M.3
Lin, J.4
Meli, A.S.5
Lamb, A.A.6
Leger, C.7
Wong, J.8
Hoffmann, H.9
Maze, D.10
Amarasinghe, S.11
-
10
-
-
33646750493
-
Practical and accurate low-level pointer analysis
-
March
-
B. Guo, M. J. Bridges, S. Triantafyllis, G. Ottoni, E. Raman, and D. I. August. Practical and accurate low-level pointer analysis. In Proceedings of the 3rd International Symposium on Code Generation and Optimization, March 2005.
-
(2005)
Proceedings of the 3rd International Symposium on Code Generation and Optimization
-
-
Guo, B.1
Bridges, M.J.2
Triantafyllis, S.3
Ottoni, G.4
Raman, E.5
August, D.I.6
-
14
-
-
4444263176
-
A study of source-level compiler algorithms for automatic construction of pre-execution code
-
D. Kim and D. Yeung. A study of source-level compiler algorithms for automatic construction of pre-execution code. ACM Trans. Comput. Syst., 22(3):326-379, 2004.
-
(2004)
ACM Trans. Comput. Syst.
, vol.22
, Issue.3
, pp. 326-379
-
-
Kim, D.1
Yeung, D.2
-
17
-
-
0031599788
-
Space-time scheduling of instruction-level parallelism on a Raw Machine
-
W. Lee, R. Barua, M. Frank, D. Srikrishna, J. Babb, V. Sarkar, and S. P. Amarasinghe. Space-time scheduling of instruction-level parallelism on a Raw Machine. In The Proceedings of the Eighth International Confrence on Architectural Support for Programming Languages and Operating Systems, pages 46-57, 1998.
-
(1998)
The Proceedings of the Eighth International Confrence on Architectural Support for Programming Languages and Operating Systems
, pp. 46-57
-
-
Lee, W.1
Barua, R.2
Frank, M.3
Srikrishna, D.4
Babb, J.5
Sarkar, V.6
Amarasinghe, S.P.7
-
18
-
-
47349091741
-
Compiler code transformations for superscalarbased high-performance systems
-
November
-
S. A. Mahlke, W. Y. Chen, J. C. Gyllenhaal, W. W. Hwu, P. P. Chang, and T. Kiyohara. Compiler code transformations for superscalarbased high-performance systems. In Proceedings of Supercomputing '92, pages 808-817, November 1992.
-
(1992)
Proceedings of Supercomputing '92
, pp. 808-817
-
-
Mahlke, S.A.1
Chen, W.Y.2
Gyllenhaal, J.C.3
Hwu, W.W.4
Chang, P.P.5
Kiyohara, T.6
-
19
-
-
33748307265
-
Rapid development of a flexible validated processor model
-
June
-
D. A. Penry, M. Vachharajani, and D. I. August. Rapid development of a flexible validated processor model. In Proceedings of the 2005 Workshop on Modeling, Benchmarking, and Simulation (MOBS), June 2005.
-
(2005)
Proceedings of the 2005 Workshop on Modeling, Benchmarking, and Simulation (MOBS)
-
-
Penry, D.A.1
Vachharajani, M.2
August, D.I.3
-
20
-
-
10444243253
-
Decoupled software pipelining with the synchronization array
-
September
-
R. Rangan, N. Vachharajani, M. Vachharajani, and D. I. August. Decoupled software pipelining with the synchronization array. In Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 177-188, September 2004.
-
(2004)
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
, pp. 177-188
-
-
Rangan, R.1
Vachharajani, N.2
Vachharajani, M.3
August, D.I.4
-
22
-
-
4644318532
-
Field-testing IMPACT EPIC research results in Itanium 2
-
J. W. Sias, S. zee Ueng, G. A. Kent, I. M. Steiner, E. M. Nystrom, and W. mei W. Hwu. Field-testing IMPACT EPIC research results in Itanium 2. In Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004.
-
(2004)
Proceedings of the 31st Annual International Symposium on Computer Architecture
-
-
Sias, J.W.1
Zee Ueng, S.2
Kent, G.A.3
Steiner, I.M.4
Nystrom, E.M.5
Mei, W.6
Hwu, W.7
-
26
-
-
33749395762
-
Multithreading decoupled architectures for complexity-effective general purpose computing
-
M. Sung, R. Krashinsky, and K. Asanovic. Multithreading decoupled architectures for complexity-effective general purpose computing. SIGARCH Comput. Archit. News, 29(5):56-61, 2001.
-
(2001)
SIGARCH Comput. Archit. News
, vol.29
, Issue.5
, pp. 56-61
-
-
Sung, M.1
Krashinsky, R.2
Asanovic, K.3
-
27
-
-
0001790593
-
Depth first search and linear graph algorithms
-
R. E. Tarjan. Depth first search and linear graph algorithms. SIAM Journal on Computing, 1(2):146-160, 1972.
-
(1972)
SIAM Journal on Computing
, vol.1
, Issue.2
, pp. 146-160
-
-
Tarjan, R.E.1
-
28
-
-
14844348900
-
Scalar operand networks
-
February
-
M. B. Taylor, W. Lee, S. P. Amarasinghe, and A. Agarwal. Scalar operand networks. IEEE Transactions on Parallel and Distributed Systems, 16(2): 145-162, February 2005.
-
(2005)
IEEE Transactions on Parallel and Distributed Systems
, vol.16
, Issue.2
, pp. 145-162
-
-
Taylor, M.B.1
Lee, W.2
Amarasinghe, S.P.3
Agarwal, A.4
-
29
-
-
0033344478
-
The superthreaded processor architecture
-
J.-Y. Tsai, J. Huang, C. Amlo, D. J. Lilja, and P.-C. Yew. The superthreaded processor architecture. IEEE Transactions on Computers, 48(9):881-902, 1999.
-
(1999)
IEEE Transactions on Computers
, vol.48
, Issue.9
, pp. 881-902
-
-
Tsai, J.-Y.1
Huang, J.2
Amlo, C.3
Lilja, D.J.4
Yew, P.-C.5
-
30
-
-
84983179859
-
Microarchitectural exploration with Liberty
-
November
-
M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August. Microarchitectural exploration with Liberty. In Proceedings of the 35th International Symposium on Microarchitecture (MICRO), pages 271-282, November 2002.
-
(2002)
Proceedings of the 35th International Symposium on Microarchitecture (MICRO)
, pp. 271-282
-
-
Vachharajani, M.1
Vachharajani, N.2
Penry, D.A.3
Blome, J.A.4
August, D.I.5
|