Single-ISA heterogeneous multi-core architectures for multithreaded workload performance

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 64-75

  Kumar, Rakesh ^a   Tullsen, Dean M ^a   Ranganathan, Parthasarathy ^b   Jouppi, Norman P ^b   Farkas, Keith I ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS (CMP); SIMULTANEOUS MULTITHREADING (SMT); SPEC; WORKLOAD;

BANDWIDTH; ENERGY EFFICIENCY; HEURISTIC METHODS; LOGIC DESIGN; MICROPROCESSOR CHIPS; MULTIPROCESSING PROGRAMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; PROGRAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 4644370318     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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