Partitioned First-Level Cache Design for Clustered Microarchitectures

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2003, Pages 22-31

  Racunas, Paul ^a   Patt, Yale N ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Clustered microarchitecture; Partitioned cache

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA TRANSFER; FORMAL LOGIC; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

CLUSTERED MICROARCHITECTURE; PARTITIONED CACHES;

CACHE MEMORY;

EID: 1142280992     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/782817.782820     Document Type: Conference Paper

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