Conjoined-core chip multiprocessing

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2004, Pages 195-206

  Kumar, Rakesh ^a   Jouppi, Norman P ^b   Tullsen, Dean M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS (CMP); FLOATING-POINT UNITS (FPU); SIMULTANEOUS MULTITHREADING (SMT); SINGLE-CHIP MULTIPROCESSORS;

BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MULTIPROCESSING SYSTEMS; TRANSISTORS;

MICROPROCESSOR CHIPS;

EID: 21644440721     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2004.12     Document Type: Conference Paper

References (15)

1. International Technology Roadmap for Semiconductors 2003, http://public.itrs.net.
2. Measuring processor performance with SPEC2000- a white paper, Intel Corporation. 2002.
3. L. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A scalable architecture based on single-chip multiprocessing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000.
4. J. Burns and I.-L. Gaudiot. Area and system clock effects on smt/cmp processors. In Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, page 211. IEEE Computer Society, 2001.
5. J. Collins and D. Tullsen. Clustered multithreaded architectures - pursuing both IPC and cycle time. In Proceedings of IPDPS, Apr. 2004.
6. R. Dolbeau and A. Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. IRISA Report 1491, Nov. 2002.
7. L. Hammond, B. A. Nayfeh, and K. Olukotun. A single-chip multiprocessor. In Computer, volume 30, pages 79-85, 1997.
8. R. Ho, K. Mai, and M. Horowitz. The future of wires. Proceedings of the IEEE, 89(4):490-504, 2001.
9. F. Karim, A. Nguyen, S. Dey, and R. Rao. On-chip communication architecture for oc-768 network processors. In Proceedings of the 2001 Design and Automation Conference, 2001.
10. V. Krishnan and J. Torrellas. A clustered approach to multithreaded processors. In Proceedings of the International Parallel Processing Symposium, pages 627-634, Mar. 1998.
11. R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. Single-ISA Heterogeneous Multi-core Architectures: The Potential for Processor Power Reduction. In International Symposium on Microarchitecture, Dec. 2003.
12. T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder. Discovering and exploiting program phases. In IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, Dec. 2003.
13. A. Snavely and D. Tullsen. Symbiotic jobscheduling for a simultaneous multithreading architecture. In Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, Nov. 2000.
14. D. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In 22nd Annual Computer Measurement Group Conference, Dec. 1996.
15. D. Tullsen, S. Eggers, and H. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In 22nd Annual International Symposium on Computer Architecture, June 1995.