메뉴 건너뛰기




Volumn , Issue , 2007, Pages 25-36

Extending multicore architectures to exploit hybrid parallelism in single-thread applications

Author keywords

[No Author keywords available]

Indexed keywords

COARSE-GRAIN THREADS; MULTICORE SYSTEMS; SINGLE-THREAD APPLICATIONS;

EID: 34547347512     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2007.346182     Document Type: Conference Paper
Times cited : (74)

References (29)
  • 8
    • 84862452827 scopus 로고    scopus 로고
    • HPL-PD architecture specification: Version 1.1
    • Technical Report HPL-93-80R.1, Hewlett-Packard Laboratories, Feb
    • V. Kathail, M. Schlansker, and B. Rau. HPL-PD architecture specification: Version 1.1. Technical Report HPL-93-80(R.1), Hewlett-Packard Laboratories, Feb. 2000.
    • (2000)
    • Kathail, V.1    Schlansker, M.2    Rau, B.3
  • 14
    • 34547653259 scopus 로고    scopus 로고
    • Extracting statistical loop-level parallelism using hardware-assisted recovery
    • Technical report, Department of Electrical Engineering and Computer Science, University of Michigan, Feb
    • S. A. Lieberman, H. Zhong, and S. A. Mahlke. Extracting statistical loop-level parallelism using hardware-assisted recovery. Technical report, Department of Electrical Engineering and Computer Science, University of Michigan, Feb 2007.
    • (2007)
    • Lieberman, S.A.1    Zhong, H.2    Mahlke, S.A.3
  • 18
    • 35048845602 scopus 로고    scopus 로고
    • Bottom-up and top-down context-sensitive summary-based pointer analysis
    • Aug
    • E. Nystrom, H.-S. Kim, and W. Hwu. Bottom-up and top-down context-sensitive summary-based pointer analysis. In Proc. of the 11th Static Analysis Symposium, pages 165-180, Aug. 2004.
    • (2004) Proc. of the 11th Static Analysis Symposium , pp. 165-180
    • Nystrom, E.1    Kim, H.-S.2    Hwu, W.3
  • 24
    • 4644353790 scopus 로고    scopus 로고
    • Evaluation of the Raw microprocessor: An exposedwire-delay architecture for ILP and streams
    • June
    • M. Taylor et al. Evaluation of the Raw microprocessor: An exposedwire-delay architecture for ILP and streams. In Proc. of the 31st Annual International Symposium on Computer Architecture, pages 2-13, June 2004.
    • (2004) Proc. of the 31st Annual International Symposium on Computer Architecture , pp. 2-13
    • Taylor, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.