Late-binding: Enabling unordered load-store queues

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 347-357

  Sethumadhavan, Simha ^a   Roesner, Franziska ^a   Emer, Joel S ^b   Burger, Doug ^a   Keckler, Stephen W ^a  

^a University of Texas at Austin   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Late binding; Memory disambiguation; Network flow control

Indexed keywords

LATE BINDING; MEMORY DISAMBIGUATION; NETWORK FLOW CONTROL; POWER EFFICIENCY;

DATA ACQUISITION; ELECTRIC LOADS; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; QUEUEING THEORY;

PROGRAM PROCESSORS;

EID: 35348816108     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250705     Document Type: Conference Paper

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