A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 9, 2004, Pages 1321-1337

  Eo, Yungseon ^a   Shin, Seongkyun ^a   Eisenstadt, William R ^b   Shim, Jongin ^a  

^a Hanyang University   (South Korea)

^b University of Florida   (United States)

Author keywords

Delay; Interconnect; Signal integrity; Signal transient; Switching pattern; Timing uncertainty; Very large scale integrated (VLSI) circuits

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CORRELATION METHODS; INDUCTANCE; PRINTED CIRCUIT DESIGN; SWITCHING; WAVEFORM ANALYSIS;

INTERCONNECT; SIGNAL INTEGRITY; SIGNAL TRANSIENT; SIGNAL-DELAYS; SWITCHING PATTERNS; TIMING UNCERTAINITY;

VLSI CIRCUITS;

EID: 4444264625     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.831571     Document Type: Article

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