On-chip interconnect evaluation on delay time increase by crosstalk

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 631-634

  Yamashita, Kyoji ^a   Odanaka, Shinji ^a   Egashira, Kyoko ^a   Ueda, Tetsuya ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CROSSTALK; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT LAYOUT; MOS CAPACITORS; OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE;

NOISE ANALYSIS; ON CHIP INTERCONNECTION; RING OSCILLATOR; WIRE LOAD;

DELAY CIRCUITS;

EID: 0033314633     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)