Figures of Merit to Characterize the Importance of On-Chip Inductance

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 560-565

  Ismail, Yehea I ^a   Friedman, Eby G ^a   Neves, Jose L ^b  

^a Department of Electrical Engineering University of Rochester ^*  (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT RESONANCE; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DAMPING; ELECTRIC LINES; INDUCTANCE; INTEGRATED CIRCUIT INTERCONNECTS; ELECTRIC IMPEDANCE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS;

CLOSED FORM SOLUTIONS; DEEP SUBMICROMETER TECHNOLOGIES; FIGURE OF MERITS; FIGURES OF MERITS; INDUCTANCE EFFECTS; INTERCONNECT LINES; ON-CHIP INDUCTANCE; RELATIVE ACCURACY;

RESONANT CIRCUITS; ELECTRIC INVERTERS;

INDUCTANCE EFFECTS;

EID: 0031622746     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277193     Document Type: Conference Paper

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