Grasping the impact of on-chip inductance

IEEE Circuits and Devices Magazine

Volumn 17, Issue 4, 2001, Pages 14-21

  Massoud, Yehia ^b   Ismail, Yehea ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

BIOT-SAVART LAW; HIGH SPEED INTEGRATED CIRCUITS; MAGNETOQUASISTATIC ASSUMPTION; ON-CHIP INDUCTANCE; PARTIAL ELEMENT EQUIVALENT CIRCUIT METHOD; SOFTWARE PACKAGE FASTHENRY;

COMPUTER SIMULATION; FINITE DIFFERENCE METHOD; FINITE ELEMENT METHOD; INTEGRAL EQUATIONS; INTERCONNECTION NETWORKS; MAXWELL EQUATIONS; PERFORMANCE; VLSI CIRCUITS;

INDUCTANCE;

EID: 0035410439     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.950046     Document Type: Article

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