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Volumn 2000-January, Issue , 2000, Pages 505-512

Deep sub-micron static timing analysis in presence of crosstalk

Author keywords

[No Author keywords available]

Indexed keywords

SPICE; SWITCHING;

EID: 0003107721     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838937     Document Type: Conference Paper
Times cited : (34)

References (9)
  • 5
    • 0030686019 scopus 로고    scopus 로고
    • Calculating worst-case gate delays due to dominant capacitance coupling
    • F. Dartu, L. T. Pileggi, "Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling", Proc. Design Automution Conference, 1997.
    • (1997) Proc. Design Automution Conference
    • Dartu, F.1    Pileggi, L.T.2
  • 7
    • 33747634671 scopus 로고    scopus 로고
    • Performance computation for precharacterized CMOS gates with RC loads
    • May
    • F. Dartu, N. Menezes, L. T. Pileggi, "Performance Computation for Precharacterized CMOS Gates with RC Loads", IEEE Trans. on Computer Aided Design, vol 15, no. 5, May 1996, pp. 544-553.
    • (1996) IEEE Trans. on Computer Aided Design , vol.15 , Issue.5 , pp. 544-553
    • Dartu, F.1    Menezes, N.2    Pileggi, L.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.