Miller factor for gate-level coupling delay calculation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 68-74

  Chen, Pinhong ^a   Kirkpatrick, Desmond A ^b   Keutzer, Kurt ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHARGE TRANSFER; CIRCUIT SIMULATION; ITERATIVE METHODS; THRESHOLD VOLTAGE; APPROXIMATION THEORY; COMPUTER SIMULATION; COUPLED CIRCUITS; CROSSTALK; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

CIRCUIT MODELING; COUPLING CAPACITANCE; EFFECTIVE CAPACITANCE; INITIAL VOLTAGES; NEWTON RAPHSON ITERATION; SPICE SIMULATIONS; STATIC TIMING ANALYSIS; SWITCHING THRESHOLD VOLTAGE;

COMPUTER AIDED DESIGN;

ACTIVE COUPLING CAPACITANCE; DECOUPLING CIRCUIT MODEL; DEEP SUBMICRON CIRCUIT; MILLER FACTOR; NEWTON-RAPHSON ITERATION; TIMING ANALYSIS;

EID: 0034483941     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896453     Document Type: Conference Paper

References (13)

1. G. Yee, R. Chandra, V. Ganesan, and C. Sechen. "Wire Delay in the Presence of Crosstalk". In IEEWACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pages 170-175, 1997.
2. B. Franzini, C. Forzan, D. Pandini, P. Scandolara, and A. D. Fabbro. "Crosstalk Aware Static Timing Analysis: A Two Step Approach". In IEEE of 1st International Symposium on Quality Electronic Design, pages 499- 503, Mar. 2000.
3. P. F. Tehrani, S. W. Chyou, and U. Ekambaram. "Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk". In IEEE of 1st Intemational Symposium on Quality Electronic Design, pages 505-5 12, Mar. 2000.
4. F. Dartu and L. T. Pileggi. "Calculating Worst-case Gate Delays Due to Dominant Capacitance Coupling". In Proc. of 34th ACMAEEE Design Automation Conference, Jun. 1997.
5. F. Dartu, N. Menezes, and L. T. Pileggi. "Performance computation for precharacterized CMOS gates with RCloads". IEEE Trans. on Computer-Aided Design of lntegrated Circuits and Systems, 15:544-553, May 1996.
6. A. B. Kahng, S. Muddu, and D. Vidhani. "Noise and Delay Estimation for Coupled RC Interconnects". In IEEE AISWSoC, Mar. 1999.
7. M. Becer and I. N. Hajj. "An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling". In IEEE of 1st International Symposium on Quality Electronic Design, pages 51-57, Mar. 2000.
8. W. Chen, S. K. Gupta, and M. A. Breuer. "AnalyticModels for Crosstalk Delay and Pulse Analysis Under Non- Ideal Inputs". In International Test Conference, pages 809-8 18, NOV. 1997.
9. T. Xiao and M. Marek-Sadowska. "Efficient Delay Calculation in Presence of Crosstalk". In IEEE of l st International Symposium on Quality Electronic Design, pages 491-497, Mar. 2000.
10. K. L. Shepard, V. Narayanan, P.C. Elmendor, and Gutuan Zheng. "Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Network". In Proc. of International Conference on Computer Aided Design, pages 139-146, 1997.
11. A. Devgan. "Efficient Coupled Noise Estimation for On- Chip Interconnects". In Proc. of International Conference on Computer Aided Design, pages 147-151, 1997.
12. K. Aringaran, F. Klass, C. M. Kim, C. Amir, J. Mitra, E. You, J. Mohd, and S. K. Dong. "Coupling Noise Analysis for VLSI and ULSI Circuits". In IEEE of 1st International Symposium on Quality Electronic Design, pages 485489, Mar. 2000.
13. A. B. Kahng, S. Muddu, and E. Sarto. "On Switch Factor Based Analysis of Coupled RC Interconnects". In Design Automation Conference, pages 79-84, 2000.