Accurate and efficient static timing analysis with crosstalk

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 265-272

  Huang, I De ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; CROSSTALK; ENCAPSULATION; LOGIC GATES; SPURIOUS SIGNAL NOISE;

CIRCUIT SIMULATION; COMBINATIONAL LOGIC; DYNAMIC TIMING ANALYSIS; GATE DELAY MODEL; ITERATIVE TIMING ANALYSIS; STATIC TIMING ANALYSIS; TIMING ITERATIVE SUBCIRCUITS;

ELECTRIC NETWORK ANALYSIS;

EID: 0036396989     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106780     Document Type: Article

References (16)

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