Dynamic thermal clock skew compensation using tunable delay buffers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 6, 2008, Pages 639-649

  Chakraborty, Ashutosh ^a,b   Duraisami, Karthik ^b   Sathanur, Ashoka ^b   Sithambaram, Prassanna ^b   Benini, Luca ^a,c   Macii, Alberto ^a,b   Macii, Enrico ^a,b   Poncino, Massimo ^a,b  

^a IEEE

^b POLITECNICO DI TORINO   (Italy)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Clock skew; Clock tree design; Temperature; Thermal design

Indexed keywords

BUFFER LAYERS; COMPUTATIONAL COMPLEXITY; NETWORKS (CIRCUITS); TEMPERATURE MEASUREMENT;

CLOCK NETWORKS; CLOCK SKEW; CLOCK TREE DESIGN; THERMAL DESIGN;

THERMAL GRADIENTS;

EID: 44249118567     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000248     Document Type: Conference Paper

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