Hybrid architectural dynamic thermal management

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 10-15

  Skadron, Kevin ^a  

^a University of Virginia   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC THERMAL MANAGEMENT (DTM); DYNAMIC VOLTAGE SCALING (DVC); INSTRUCTION LEVEL PARALLELISM (ILP); ON-CHIP SENSORS; COOLING CAPACITY; DYNAMIC THERMAL MANAGEMENT; DYNAMIC VOLTAGE SCALING; ENVIRONMENTAL CONDITIONS; EXECUTION SPEED; HYBRID POLICIES; INSTRUCTION-LEVEL PARALLELISM; OPERATING TEMPERATURE;

CHIP SCALE PACKAGES; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; COOLING; FEEDBACK CONTROL; HEAT LOSSES; LAPTOP COMPUTERS; MICROPROCESSOR CHIPS; VOLTAGE CONTROL; COST REDUCTION; DESIGN; EXHIBITIONS; THERMAL STRESS; VOLTAGE STABILIZING CIRCUITS;

HYBRID COMPUTERS; TEMPERATURE CONTROL;

EID: 3042565511     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268820     Document Type: Conference Paper

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