Activity-driven clock design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 6, 2001, Pages 705-714

  Farrahi, Amir H ^a,b   Chen, Chunhong ^a,c   Srivastava, Ankur ^a,c   Téllez, Gustavo ^d   Sarrafzadeh, Majid ^a,c  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c University of California   (United States)

^d IBM   (United States)

Author keywords

Activity driven clock design; Algorithms; Clock gating; Clock tree; Power optimization; Zero skew clock

Indexed keywords

ACTIVITY DRIVEN CLOCK DESIGN; APPROXIMATION ALGORITHM; CLOCK GATE INSERTION PROBLEM; CLOCK TREE CONSTRUCTION PROBLEM; CLOCK TREE GATING; CLOCK TREES; RECURSIVE MATCHING; ZERO SKEW CLOCK GATE INSERTION PROBLEM;

ALGORITHMS; APPROXIMATION THEORY; COMPUTER AIDED DESIGN; DYNAMIC PROGRAMMING; LOGIC GATES; THEOREM PROVING;

TIMING CIRCUITS;

EID: 0035369246     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.924824     Document Type: Article

References (21)

1. A survey of heuristics for the weighted matching problem
2. Zero-skew clock routing with minimum wirelength
3. A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI and WSI circuits
4. Wire length and delay minimization in general clock net routing
5. Zero skew clock net routing
6. Zero skew clock routing with minimum wirelength
7. A clustering-based optimization algorithm in zero-skew routings
8. Delay minimization for zero-skew routing
9. Clock distribution design in VLSI circuits-An overview
10. An efficient implementation of Edmonds' algorithm for maximum matching on graphs
11. Clock routing for high-performance ICs
12. High-performance clock routing based on recursive geometric matching
13. GORDIAN: VLSI placement by quadratic programming and slicing optimization
14. Skew and delay optimization for reliable buffered clock trees
15. Reliable nonzero skew clock tree using wire width optimization
16. The TimberWolf placement and routing package
17. Effective buffer insertion of clock tree for high speed VLSI circuits
18. Exact zero skew