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Volumn 11, Issue 4, 2003, Pages 616-626

A Clock-Tuning Circuit for System-on-Chip

Author keywords

Circuit tuning; Clock distribution; Inserted delay; Intellectual property (IP) core; System on chip (SoC)

Indexed keywords

HIERARCHICAL SYSTEMS; INTELLECTUAL PROPERTY; SYNCHRONIZATION; TUNING;

EID: 0141862183     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812371     Document Type: Article
Times cited : (19)

References (22)
  • 5
    • 0008574012 scopus 로고    scopus 로고
    • The meta-methods: Managing design risk during IP selection and integration
    • C. K. Lennard and E. Granata, "The meta-methods: Managing design risk during IP selection and integration," in Proc. IP 1999 Europe, pp. 285-299.
    • (1999) Proc. IP 1999 Europe , pp. 285-299
    • Lennard, C.K.1    Granata, E.2
  • 7
    • 0003850954 scopus 로고    scopus 로고
    • Digital Integrated Circuits a Design Perspective
    • Englewood, NJ: Prentice-Hall
    • J. M. Rabaey, Digital Integrated Circuits a Design Perspective. Englewood, NJ: Prentice-Hall, 1996, Prentice-Hall Electronics and VLSI series.
    • (1996) Prentice-hall Electronics and VLSI Series
    • Rabaey, J.M.1
  • 8
    • 0025502944 scopus 로고
    • Synchronization in digital system design
    • Oct.
    • D. G. Messerschmitt, "Synchronization in digital system design," IEEE J. Selected Areas Commun., vol. 8, pp. 1404-1419, Oct. 1990.
    • (1990) IEEE J. Selected Areas Commun. , vol.8 , pp. 1404-1419
    • Messerschmitt, D.G.1
  • 9
    • 0005468712 scopus 로고    scopus 로고
    • Los Gatos, CA. [Online]
    • VSI Alliance Architecture Document. VSI Alliance, Los Gatos, CA. [Online]. Available: http://www.vsi.org/library/specs/summary.htm
    • VSI Alliance Architecture Document
  • 10
    • 0033221575 scopus 로고    scopus 로고
    • Rethinking deep-submicron circuit design
    • Nov.
    • D. Sylvester and K. Keutzer, "Rethinking deep-submicron circuit design," IEEE Computer, pp. 25-33, Nov. 1999.
    • (1999) IEEE Computer , pp. 25-33
    • Sylvester, D.1    Keutzer, K.2
  • 11
    • 33646922057 scopus 로고    scopus 로고
    • The future of wires
    • Apr.
    • R. Ho, K. W. Mai, and M. Horowitz, "The future of wires," Proc. IEEE, vol. 89, pp. 490-504, Apr. 2001.
    • (2001) Proc. IEEE , vol.89 , pp. 490-504
    • Ho, R.1    Mai, K.W.2    Horowitz, M.3
  • 12
    • 0032206398 scopus 로고    scopus 로고
    • Clocking design and analysis for a 600-MHz alpha, microprocessor
    • Nov.
    • D. W. Baily and B. J. Benschneider, "Clocking design and analysis for a 600-MHz alpha, microprocessor," IEEEJ. Solid-State Circuits, vol. 33, pp. 1627-1633, Nov. 1998.
    • (1998) IEEEJ. Solid-state Circuits , vol.33 , pp. 1627-1633
    • Baily, D.W.1    Benschneider, B.J.2
  • 13
    • 0031678276 scopus 로고
    • A noise-immune GHz-clock distribution scheme using synchronous oscillators
    • H. Mizuno and K. Ishibashi, "A noise-immune GHz-clock distribution scheme using synchronous oscillators," in Proc. IEEE Int. Solid-State Circuits Conf., 1988, pp. 404-405.
    • (1988) Proc. IEEE Int. Solid-state Circuits Conf. , pp. 404-405
    • Mizuno, H.1    Ishibashi, K.2
  • 16
    • 0034317260 scopus 로고    scopus 로고
    • The first IA-64 microprocessor
    • Nov.
    • S. Rusu and G. Singer, "The first IA-64 microprocessor," IEEE J. Solid-State Circuits, vol. 35, pp. 1539-1544, Nov. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1539-1544
    • Rusu, S.1    Singer, G.2
  • 17
    • 0034317347 scopus 로고    scopus 로고
    • Clock generation and distribution for the first IA-64 microprocessor
    • Nov.
    • S. Tam, S. Rusu, U. N. Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. Solid-State Circuits, vol. 35, pp. 1545-1552, Nov. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1545-1552
    • Tam, S.1    Rusu, S.2    Desai, U.N.3    Kim, R.4    Zhang, J.5    Young, I.6
  • 18
    • 0033280316 scopus 로고    scopus 로고
    • Statistical analysis of timing rules for high speed synchronous VLSI systems
    • Dec.
    • C. -S. Li, K. N. Sivarajan, and D. Messerschmitt, "Statistical analysis of timing rules for high speed synchronous VLSI systems," IEEE Trans. VLSI Syst., vol. 7, pp. 477-482, Dec. 1999.
    • (1999) IEEE Trans. VLSI Syst. , vol.7 , pp. 477-482
    • Li, C.-S.1    Sivarajan, K.N.2    Messerschmitt, D.3
  • 19
    • 0034316214 scopus 로고    scopus 로고
    • Active GHz clock network using distributed PLL's
    • Nov.
    • V. Gutnik and A. P. Chandrakasan, "Active GHz clock network using distributed PLL's," IEEE J. Solid-State Circuits, vol. 35, pp. 1553-1560, Nov. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1553-1560
    • Gutnik, V.1    Chandrakasan, A.P.2
  • 20
    • 0030287146 scopus 로고    scopus 로고
    • A 2.5-ns clock access, 250 MHz, 256-Mb SDRAM with synchronous mirror delay
    • Nov.
    • T. Saeki, "A 2.5-ns clock access, 250 MHz, 256-Mb SDRAM with synchronous mirror delay," IEEE J. Solid-State Circuits, vol. 30, pp. 1656-1668, Nov. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.30 , pp. 1656-1668
    • Saeki, T.1
  • 21
    • 0035334849 scopus 로고    scopus 로고
    • A clock distribution network for microprocessors
    • May
    • P. J. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, pp. 792-797, May 2001.
    • (2001) IEEE J. Solid-state Circuits , vol.36 , pp. 792-797
    • Restle, P.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.