A yield improvement methodology using pre- and post-silicon statistical clock scheduling

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 611-618

  Tsai, Jeng Liang ^a   Baik, Donghyun ^a   Chen, Charlie Chung Ping ^b   Saluja, Kewal K ^a  

^a University of Wisconsin Madison   (United States)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SCHEDULING; CLOCK SKEWS; DELAY-FAULT TESTING; STATISTICAL TIMING ANALYSIS;

ALGORITHMS; DELAY CIRCUITS; INFORMATION ANALYSIS; LINEAR PROGRAMMING; SCHEDULING; SILICON; STATISTICAL METHODS; TIMING CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 16244383507     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

1. Stephan Held, Bernhard Korte, Jens Maberg, Matthias Ringe, and J. Vygen. Clock scheduling and clocktree construction for high performance asics. In Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, pages 232-239, 2003.
2. C. Albrecht, B. Korte, J. Schietke, and J. Vygen. Cycle time and slack optimization for VLSI-chips. In Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, pages 232-238, 1999.
3. John P. Fishburn. Clock skew optimization. IEEE Transactions on Computers, 39(7):945-951, July 1990.
4. Rahul B. Deokar and Sachin S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, volume 1, pages 407-410, May 1995.
5. José Luis Neves and Eby G. Friedman. Optimal clock skew scheduling tolerant to process variations. In Proceedings of the 33rd annual conference on Design automation conference, pages 623-628, 1996.
6. Ivan S. Kourtev and Eby G. Friedman. Clock skew scheduling for improved reliability via quadratic programming. In Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, pages 239-243, 1999.
7. N. E. Young, Robert E. Tarjan, and J. B. Orlin. Faster parametric shortest path and minimum-balance algorithms. Networks, 21:205-221, 1991.
8. Utpal Desai, Simon Tam, Robert Kim, Ji Zhang, and Stefan Rusu. Itanium processor clock design. In Proceedings of the 2000 international symposium on Physical design, pages 94-98, 2000.
9. Jason Stinson and Stefan Rusu. A 1.5GHz third generation Itanium-2 processor. In Proceedings of the 40th conference on Design automation, pages 706-709, 2003.
10. R. Ginosar, Y. Elboim, and A. Kolodny. A clock tuning circuit for system-on-chip. In Proceedings of the second ACiD-WG workshop of the european commission's fifth framework programme, 2002.
11. E. Takahashi, Y. Kasai, M. Murakawa, and T. Higuchi. A post-silicon clock timing adjustment using genetic algorithms. In Digest of technical papers of the 2003 symposium on VLSI circuits, pages 13-16, 2003.
12. Kwang-Ting Cheng and H-C. Chen. Delay testing for non-robust untestable circuits. In International Test Conference, pages 954-961, Oct 1993.
13. Karl Fuchs, Franz Fink, and Michael H. Schulz. DYNAMITE: An efficient automatic test pattern generation system for path delay faults. IEEE Transactions on Computer-aided design, 10(10):1323-1335, Oct 1991.
14. Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, and Sudhakar M. Reddy. A method for identifying robust dependent and functionally unsensitizable paths. In 10th International Conference on VLSI Design, pages 82-87, Jan 1996.
15. Jing-Jia Liou, Angela Krstic, Li-C. Wang, and Kwang-Ting Cheng. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. In Proceedings of the 39th conference on Design automation, pages 566-569, 2002.
16. K.-T. Cheng and H.-C. Chen. Delay testing for non-robust untestable circuits. In Proceedings of the International test conference, pages 954-961, Oct 1993.
17. R. Bellman. On a routing problem. Quarterly of Applied Mathematics, 6(1):87-90, 1958.
18. L. R. Ford and D. R. Fulkerson. Flows in networks. Princeton University Press, 1962.
19. G.B. Dantzig. Linear Programming and Extensions. Princeton University Press, Princeton, N.J., 1963.
20. Daniel Spielman and Shang-Hua Teng. Smoothed analysis of algorithms: why the simplex algorithm usually takes polynomial time. In Proceedings of the thirty-third annual ACM symposium on Theory of computing, pages 296-305, 2001.
21. Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, and Ian Young. Clock generation and distribution for the first IA-64 microprocessor. IEEE Journal of Solid-State Circuits, 35(11):1545-1552, Nov 2000.
22. David Harris and Sam Naffziger. Statistical clock skew modeling with data delay variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(6):888-898, Dec 2001.
23. C. J. Line, S. M. Reddy, and S. K. Sahni. On delay fault testing in logic circuits. IEEE Transactions on Computer-aided design, CAD-6(5):694-703, Jan 1987.
24. K. Fuchs, M. Pabst, and T. Rossel. RESIST: A recursive test pattern generation algorithm for path delay faults considering various test classes. IEEE Transactions on Computer-aided design, 13(12):1550-1562, Dec 1994.
25. S. Padmanaban and S. Tragoudas. An implicit path-delay diagnosis methodology. IEEE Transactions on Computer-aided design, 22(10):1399-1408, Oct 2003.
26. P. Girard, C. Landrault, and S. Pravossoudovitch. An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Testing, 6(3):277-293, 1995.
27. S. DasGupta, R. G. Walther, and T. W. Williams. An enhancement to LSSD and some applications of LSSD in reliability. In Proceedings of the International test symposium, pages 32-34, Jun 1981.