Clock-tree power optimization based on RTL clock-gating

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 622-627

  Donno, Monica ^a   Ivaldi, Alessandro ^b   Benini, Luca ^c   Macii, Enrico ^b  

^a R and D Division   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Clock tree synthsis; Low power design

Indexed keywords

PRODUCT DESIGN; SILICON; TREES (MATHEMATICS);

CLOCK TREE;

VLSI CIRCUITS;

EID: 0042134691     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775989     Document Type: Conference Paper

References (12)

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