Zero Skew Clock-Tree Optimization with Buffer Insertion/Sizing and Wire Sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 4, 2004, Pages 565-572

  Tsai, Jeng Liang ^a   Chen, Tsung Hao ^a   Chen, Charlie Chung Ping ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Buffer insertion; Buffer sizing; Clock tree; Optimization; Wire sizing; Zero skew

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; DELAY CIRCUITS; ELECTRIC CLOCKS; OPTIMIZATION; POLYNOMIALS; TREES (MATHEMATICS); VLSI CIRCUITS;

BUFFER INSERTION; BUFFER SIZING; CLOCK TREE; WIRE SIZING; ZERO SKEW;

INTEGRATED CIRCUIT LAYOUT;

EID: 2342423095     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.825875     Document Type: Conference Paper

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