A Post-silicon Clock Timing Adjustment Using Genetic Algorithms

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 13-16

  Takahashi, Eiichi ^a   Kasai, Yuji ^a   Murakawa, Masahiro ^a   Higuchi, Tetsuya ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

Clock enhancement; Clock timing adjustment; Genetic algorithm; Lowering power supply voltage; Operating yield improvement; Post silicon adjustment; Reduced design time; Reduced power dissipation

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ELECTRIC POWER SUPPLIES TO APPARATUS; GENETIC ALGORITHMS; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

CLOCK TIMING ADJUSTMENT;

LSI CIRCUITS;

EID: 0141538283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. E. Takahashi, M. Murakawa, K. Toda, T. Higuchi, "An Evolvable-Hardware-based Clock Architecture towards GigaHz Digital Systems," Proc. of AAAI GECCO'99(Genetic Algorithm and Evolutionary Computation Conference), pp.1204-1210, July 1999.
2. D. Deleganes, J. Douglas, B. Kommandaur, M. Patyra, "Design a 3GHz, 130nm, Pentium4 Processor," Proc. of 2002 Symposium on VLSI Circuits, Feb. 2002.
3. T. Higuchi, et al. "Real-World Applications of Analog and Digital Evolvable Hardware," IEEE Transactions of Evolutionary Computation, vol. 3, pp. 220-235, 1999.
4. T. Sakurai, "LSI design toward 2010 low-power technology," International Conference on VLSI & CAD '99, pp.325-334, Oct. 1999.