TACO: Temperature aware clock-tree optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 582-587

  Cho, Minsik ^a   Ahmed, Suhail ^a,b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; MICROPROCESSOR CHIPS; OPTIMIZATION; ROUTERS; THERMAL EFFECTS;

CLOCK SKEW; CLOCK TREE WIRELENGTH; LINEAR TIME ALGORITHM; TEMPERATURE AWARE CLOCK TREE OPTIMIZATION;

COMPUTER AIDED DESIGN;

EID: 33751399739     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560133     Document Type: Conference Paper

References (20)

1. International Technology Roadmap for Semiconductors (ITRS), 2003.
2. Q. Wu, Q. Qiu, and M. Pedram, "Dynamic power management of complex systems using generalized stochastic Petri nets," in Proc. Design Automation Conf., Jun 2000.
3. J. Oh and M. Pedram, "Gated clock routing for low-power microprocessor design," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 715-722, Jun 2001.
4. R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. H. Kulkarni, "Pushing ASIC Performance in a Power Envelope," in Proc. Design Automation Conf., 2003.
5. A. Srivastava, D. Sylvester, and D. Blaauw, "Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design," in Proc. Design, Automation and Test in Eurpoe, vol. 1, Feb 2004, pp. 718-719.
6. J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology," in Proc. Design Automation Conf., 1997.
7. C. Long and L. He, "Distributed sleep transistor network for power reduction," in Proc. Design Automation Conf, 2003.
8. P. Gronowski et al., "High performance microprocessor design," IEEE J. Solid-State Circuits, vol. 33, pp. 676-686, May 1998.
9. S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-d) and vertically integrated (3-d) high performance ICs," in Tech. Dig. IEEE International Electron Devices Meeting, Dec 2000.
10. T.-Y. Chiang, B. Shieh, and K. Sarawat, "Impact of Joule heating on scaling of deep sub-micron Cu/low-k interconnects," in Symposium on VLSI Technology, Digest of Technical Papers, Jun 2002, pp. 38-39.
11. P. Wilkerson, A. Raman, and M. Turowski, "Fast, automated thermal simulation of three-dimensional integrated circuits," in Inter Society Conference on Thermal Phenomena, vol. 1, Jun 2004, pp. 706-713.
12. F. Chen, J. Gill, and D. Harmon, "Measurements of effective thermal conductivity for advanced interconnect structure with various composite low-k dielectrics," in International Reliability Physics Symposium, 2004.
13. A. H. Ajami, M. Pedram, and K. Banergee, "Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs," in Proc. IEEE Custom Integrated Circuits Conf.
14. K. Banergee, A. H. Ajami, and M. Pedram, "Analysis and optimization of thermal issues in high-performance VLSI," in Proc. Int. Symp. on Physical Design, April 2001, pp. 230-237.
15. K. D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wirelength," in Proc. IEEE Int. Conf. ASIC.
16. J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao, "Bounded-Skew Clock and Steiner Routing," ACM Trans. on Design Automation of Electronics Systems, vol. 4, no. 1, Jan 1999.
17. R.-S. Tsay, "An Exact Zero Skew Clock Routing Algorithm," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 242-249, Feb 1993.
18. T. Wang and C. C. Chen, "3D Thermal-ADI: A linear-time chip level transient thermal simulator," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 12, Dec 2002.
19. http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/BST/.
20. T. Wang and C. Chen, "Power-Delivery Networks Optimization with Thermal Reliability Integrity," in Proc. Int. Symp. on Physical Design, April 2004.