Clock distribution on a dual-core, multi-threaded itanium®-family processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Mahoney, Patrick ^a   Fetzer, Eric ^a   Doyle, Bruce ^a   Naffziger, Sam ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144460650     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Naffziger et al., "The Implementation of a 2-core, Multi-threaded Itanium®Family Processor," ISSCC Dig. Tech. Papers, Paper 10.1, pp. 182-183, Feb., 2005.
2. Raphael User Manual, Avant! Corporation
3. Ferd Anderson et al., "The Core clock System on the Next Generation Itanium® Microprocessor," ISSCC Dig. Tech. Papers, vol. 1, pp. 146-148, Feb., 2002.