An instruction throughput model of superscalar processors

Proceedings of the International Workshop on Rapid System Prototyping

Volumn 2003-January, Issue , 2003, Pages 156-163

  Taha, T M ^a   Wills, D S ^b  

^a AMRL   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Buildings; Computer architecture; Current supplies; Microarchitecture; Out of order; Process design; Space technology; Throughput; Thumb; Time to market

Indexed keywords

ARCHITECTURAL DESIGN; BUILDINGS; COMMERCE; COMPUTER ARCHITECTURE; CONCURRENT ENGINEERING; DELAY CONTROL SYSTEMS; DESIGN; PROCESS DESIGN; SEMICONDUCTOR DEVICE MANUFACTURE; SIMULATORS; THROUGHPUT;

CURRENT SUPPLIES; MICRO ARCHITECTURES; OUT OF ORDER; SPACE TECHNOLOGIES; THUMB; TIME TO MARKET;

INTEGRATED CIRCUIT DESIGN;

EID: 43049086134     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWRSP.2003.1207043     Document Type: Conference Paper

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