The effect of instruction window on the performance of superscalar processors

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E81-A, Issue 6, 1998, Pages 1036-1044

  Pyun, Yong Hycon ^a   Park, Choung Shik ^a   Choi, Sang Bang ^a  

^a Inha University   (South Korea)

Author keywords

In order issue; Instruction issue rate; Instruction window; Outof order issue; Superscalar

Indexed keywords

CALCULATIONS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SOFTWARE; ESTIMATION; MATHEMATICAL MODELS; PERFORMANCE;

BENCHMARK PROGRAM; IN ORDER ISSUE; INSTRUCTION ISSUE RATE; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION WINDOW; OUT ORDER ISSUE; SUPERSCALAR PROCESSOR;

MICROPROCESSOR CHIPS;

EID: 0032094088     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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