An analytical model for Trace Cache instruction fetch performance

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 477-480

  Hossain, Afzal ^a   Pease, Daniel J ^a  

^a Syracuse University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROBABILITY;

MICROARCHITECTURE;

CACHE MEMORY;

EID: 0035181795     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955069     Document Type: Article

References (4)

1. A Trace Cache microarchitecture and evaluation
2. Modeled and measured instruction fetching performance for superscalar microprocessors
3. The working-set model for program behaviour
4. Simultaneous multithreading: A platform for next-generation processors