Modeling architectural improvements in superscalar processors

Proceedings - 4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

Volumn 1, Issue , 2000, Pages 28-30

  Zhu, Y ^a   Wong, W F ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING;

ARCHITECTURAL IMPROVEMENTS; AVERAGE ERRORS; FUNCTIONAL UNITS; MULTIPLE CLASS; MULTIPLE RESOURCES; SUPERSCALAR PROCESSOR;

COMPUTER SCIENCE;

EID: 33746901663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPC.2000.846511     Document Type: Conference Paper

References (7)

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3. Loh, K. S. (1997). 'Superscaler Processor Simulator', Honour Year Project Report, Dept. of Information Systems and Computer Science, National University of Singapore.
4. Noonburg, D. B., and Shen, J. P. (1994). 'Theoretical Modeling of Superscalar Processor Performance', Proc. of MICRO 27, pp. 53-62, San Jose, USA.
5. Pyun, Y.H., Park, C.S., Choi, S.B. (1998). 'The effect of instruction window on the performance of superscalar processors', IEICE Trans. on Fund. of Elec. Comms. & Comp. Sc., E81A: (6) 1036-1044 JUN 1998
6. Zhu, Y., and Wong, W. F. (1997). 'Performance Analysis of Superscalar Processor Using a Queueing Model', Proc. of Comp. Arch. '97: The 2nd Australasian Conference, pp. 147-158, Sydney, Australia, Springer-Verlag.
7. Zhu, Y., and Wong, W. F. (1998). 'The Effect of Instruction Dependency on Superscalar Processor Performance' Aust. Comp. Sc. Comms., pp. 215-226, Volume 20, Number 4, Springer-Verlag.